Replace Signal(bits_for(... with Signal(max=...

This commit is contained in:
Sebastien Bourdeauducq 2012-11-29 23:41:51 +01:00
parent 8bf6945dfd
commit 293a62dabe
3 changed files with 5 additions and 5 deletions

View file

@ -42,7 +42,7 @@ class _Selector:
self.nslots = len(self.slots) self.nslots = len(self.slots)
self.stb = Signal() self.stb = Signal()
self.ack = Signal() self.ack = Signal()
self.tag = Signal(bits_for(self.nslots-1)) self.tag = Signal(max=self.nslots)
self.adr = Signal(self.slots[0].adr.nbits) self.adr = Signal(self.slots[0].adr.nbits)
self.we = Signal() self.we = Signal()
@ -238,7 +238,7 @@ class BankMachine:
# Respect write-to-precharge specification # Respect write-to-precharge specification
precharge_ok = Signal() precharge_ok = Signal()
t_unsafe_precharge = 2 + self.timing_settings.tWR - 1 t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
unsafe_precharge_count = Signal(bits_for(t_unsafe_precharge)) unsafe_precharge_count = Signal(max=t_unsafe_precharge+1)
comb.append(precharge_ok.eq(unsafe_precharge_count == 0)) comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
sync += [ sync += [
If(self.cmd.stb & self.cmd.ack & self.cmd.is_write, If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,

View file

@ -64,7 +64,7 @@ class _Steerer:
ncmd = len(self.commands) ncmd = len(self.commands)
nph = len(self.dfi.phases) nph = len(self.dfi.phases)
self.sel = [Signal(bits_for(ncmd-1)) for i in range(nph)] self.sel = [Signal(max=ncmd) for i in range(nph)]
def get_fragment(self): def get_fragment(self):
comb = [] comb = []
@ -194,7 +194,7 @@ class Multiplexer:
max_time = Signal() max_time = Signal()
if timeout: if timeout:
t = timeout - 1 t = timeout - 1
time = Signal(bits_for(t)) time = Signal(max=t+1)
comb.append(max_time.eq(time == 0)) comb.append(max_time.eq(time == 0))
sync.append( sync.append(
If(~en, If(~en,

View file

@ -45,7 +45,7 @@ class Refresher:
]) ])
# Periodic refresh counter # Periodic refresh counter
counter = Signal(bits_for(self.tREFI - 1)) counter = Signal(max=self.tREFI)
start = Signal() start = Signal()
sync += [ sync += [
start.eq(0), start.eq(0),