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Replace Signal(bits_for(... with Signal(max=...
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8bf6945dfd
commit
293a62dabe
3 changed files with 5 additions and 5 deletions
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@ -42,7 +42,7 @@ class _Selector:
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self.nslots = len(self.slots)
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self.stb = Signal()
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self.ack = Signal()
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self.tag = Signal(bits_for(self.nslots-1))
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self.tag = Signal(max=self.nslots)
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self.adr = Signal(self.slots[0].adr.nbits)
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self.we = Signal()
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@ -238,7 +238,7 @@ class BankMachine:
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# Respect write-to-precharge specification
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precharge_ok = Signal()
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t_unsafe_precharge = 2 + self.timing_settings.tWR - 1
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unsafe_precharge_count = Signal(bits_for(t_unsafe_precharge))
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unsafe_precharge_count = Signal(max=t_unsafe_precharge+1)
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comb.append(precharge_ok.eq(unsafe_precharge_count == 0))
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sync += [
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If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,
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@ -64,7 +64,7 @@ class _Steerer:
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ncmd = len(self.commands)
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nph = len(self.dfi.phases)
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self.sel = [Signal(bits_for(ncmd-1)) for i in range(nph)]
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self.sel = [Signal(max=ncmd) for i in range(nph)]
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def get_fragment(self):
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comb = []
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@ -194,7 +194,7 @@ class Multiplexer:
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max_time = Signal()
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if timeout:
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t = timeout - 1
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time = Signal(bits_for(t))
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time = Signal(max=t+1)
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comb.append(max_time.eq(time == 0))
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sync.append(
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If(~en,
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@ -45,7 +45,7 @@ class Refresher:
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])
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# Periodic refresh counter
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counter = Signal(bits_for(self.tREFI - 1))
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counter = Signal(max=self.tREFI)
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start = Signal()
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sync += [
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start.eq(0),
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