cores/jtag/ECP5JTAG: Fix LUT4's INIT to create a buffer instead of inverter, thanks @gregdavill.

Avoid restriction to even number for tck_delay_luts.
2025-01-04 09:52:26 -05:00 · 2021-10-27 11:01:09 +02:00 · 2021-10-27 11:01:09 +02:00 · 296688b2d8
commit 296688b2d8
parent 0b40d78b0d
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/jtag.py
+++ b/litex/soc/cores/jtag.py
@ -128,7 +128,7 @@ class ECP5JTAG(Module):
            new_tck = Signal()
            self.specials += Instance("LUT4",
                attr   = {"keep"},
-                p_INIT = 1,
+                p_INIT = 2,
                i_A = tck,
                i_B = 0,
                i_C = 0,