Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cores/spi/spi_bone: Remove some duplicated code between 2 and 3 wires cases.

This commit is contained in:
Florent Kermarrec 2022-10-19 10:53:26 +02:00
parent eabdc0b7e9
commit 2a15ab554a
1 changed files with 5 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
litex/soc/cores/spi/spi_bone.py
View File

@ -167,21 +167,16 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
sync_byte = Signal(8)
self.specials += MultiReg(pads.clk, clk)
if wires in [2, 3]:
io = TSTriple()
self.specials += io.get_tristate(pads.mosi)
self.specials += MultiReg(io.i, mosi)
self.comb += io.o.eq(miso)
self.comb += io.oe.eq(miso_en)
if wires == 2:
io = TSTriple()
self.specials += io.get_tristate(pads.mosi)
self.specials += MultiReg(io.i, mosi)
self.comb += io.o.eq(miso)
self.comb += io.oe.eq(miso_en)
if wires == 3:
self.specials += MultiReg(pads.cs_n, cs_n),
io = TSTriple()
self.specials += io.get_tristate(pads.mosi)
self.specials += MultiReg(io.i, mosi)
self.comb += io.o.eq(miso)
self.comb += io.oe.eq(miso_en)
if wires == 4:
self.specials += MultiReg(pads.cs_n, cs_n),
self.specials += MultiReg(pads.cs_n, cs_n)
if wires in [4]:
self.specials += MultiReg(pads.cs_n, cs_n)
self.specials += MultiReg(pads.mosi, mosi)
if with_tristate:
self.specials += Tristate(pads.miso, miso, ~cs_n)