cores/spi/spi_bone: Remove some duplicated code between 2 and 3 wires cases.
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@ -167,21 +167,16 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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sync_byte = Signal(8)
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self.specials += MultiReg(pads.clk, clk)
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if wires in [2, 3]:
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io = TSTriple()
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self.specials += io.get_tristate(pads.mosi)
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self.specials += MultiReg(io.i, mosi)
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self.comb += io.o.eq(miso)
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self.comb += io.oe.eq(miso_en)
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if wires == 2:
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io = TSTriple()
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self.specials += io.get_tristate(pads.mosi)
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self.specials += MultiReg(io.i, mosi)
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self.comb += io.o.eq(miso)
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self.comb += io.oe.eq(miso_en)
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if wires == 3:
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self.specials += MultiReg(pads.cs_n, cs_n),
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io = TSTriple()
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self.specials += io.get_tristate(pads.mosi)
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self.specials += MultiReg(io.i, mosi)
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self.comb += io.o.eq(miso)
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self.comb += io.oe.eq(miso_en)
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if wires == 4:
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self.specials += MultiReg(pads.cs_n, cs_n),
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self.specials += MultiReg(pads.cs_n, cs_n)
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if wires in [4]:
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self.specials += MultiReg(pads.cs_n, cs_n)
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self.specials += MultiReg(pads.mosi, mosi)
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if with_tristate:
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self.specials += Tristate(pads.miso, miso, ~cs_n)
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