Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen

This commit is contained in:
Florent Kermarrec 2018-09-07 10:37:15 +02:00
parent 26963d62fa
commit 2b786065b1
7 changed files with 15 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex/boards/targets/arty.py
View File

@ -136,7 +136,8 @@ class MiniSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
self.platform.request("eth")) self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness="little") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu_endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)

3
litex/boards/targets/genesys2.py
View File

@ -118,7 +118,8 @@ class MiniSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth")) self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu_endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)

3
litex/boards/targets/kc705.py
View File

@ -118,7 +118,8 @@ class MiniSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"), self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
self.platform.request("eth"), clk_freq=self.clk_freq) self.platform.request("eth"), clk_freq=self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu_endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)

3
litex/boards/targets/nexys_video.py
View File

@ -125,7 +125,8 @@ class MiniSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth")) self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu_endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)

3
litex/boards/targets/sim.py
View File

@ -87,7 +87,8 @@ class MiniSoC(BaseSoC):
BaseSoC.__init__(self, *args, **kwargs) BaseSoC.__init__(self, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu_endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)

3
litex/boards/targets/simple.py
View File

@ -45,8 +45,7 @@ class MiniSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth")) platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", interface="wishbone", endianness=self.cpu_endianness, with_preamble_crc=False)
with_preamble_crc=False)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)

7
litex/soc/software/libnet/microudp.c
View File

@ -127,6 +127,7 @@ static ethernet_buffer *txbuffer1;
static void send_packet(void) static void send_packet(void)
{ {
#ifndef HW_PREAMBLE_CRC #ifndef HW_PREAMBLE_CRC
unsigned int crc; unsigned int crc;
crc = crc32(&txbuffer->raw[8], txlen-8); crc = crc32(&txbuffer->raw[8], txlen-8);
@ -134,9 +135,9 @@ static void send_packet(void)
txbuffer->raw[txlen+1] = (crc & 0xff00) >> 8; txbuffer->raw[txlen+1] = (crc & 0xff00) >> 8;
txbuffer->raw[txlen+2] = (crc & 0xff0000) >> 16; txbuffer->raw[txlen+2] = (crc & 0xff0000) >> 16;
txbuffer->raw[txlen+3] = (crc & 0xff000000) >> 24; txbuffer->raw[txlen+3] = (crc & 0xff000000) >> 24;
//txlen += 4; txlen += 4;
#endif #endif
txlen += 4; // FIXME txlen += 4; //FIXME: padding?
#ifdef DEBUG_MICROUDP_TX #ifdef DEBUG_MICROUDP_TX
int j; int j;
@ -169,7 +170,7 @@ static void process_arp(void)
const struct arp_frame *rx_arp = &rxbuffer->frame.contents.arp; const struct arp_frame *rx_arp = &rxbuffer->frame.contents.arp;
struct arp_frame *tx_arp = &txbuffer->frame.contents.arp; struct arp_frame *tx_arp = &txbuffer->frame.contents.arp;
//if(rxlen < ARP_PACKET_LENGTH) return; // FIXME if(rxlen < ARP_PACKET_LENGTH) return;
if(ntohs(rx_arp->hwtype) != ARP_HWTYPE_ETHERNET) return; if(ntohs(rx_arp->hwtype) != ARP_HWTYPE_ETHERNET) return;
if(ntohs(rx_arp->proto) != ARP_PROTO_IP) return; if(ntohs(rx_arp->proto) != ARP_PROTO_IP) return;
if(rx_arp->hwsize != 6) return; if(rx_arp->hwsize != 6) return;