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targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)

This commit is contained in:
Florent Kermarrec 2015-03-06 07:51:44 +01:00
parent 52f1c45407
commit 2b9397ff5b
6 changed files with 119 additions and 109 deletions
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5
misoclib/soc/sdram.py
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@ -70,6 +70,7 @@ class SDRAMSoC(SoC):
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
def do_finalize(self): def do_finalize(self):
if not self._sdram_phy_registered: if not self.with_sdram:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()") if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
SoC.do_finalize(self) SoC.do_finalize(self)

43
targets/de0nano.py
View File

@ -87,28 +87,29 @@ class BaseSoC(SDRAMSoC):
with_rom=True, with_rom=True,
**kwargs) **kwargs)
sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=13,
col_a=9
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(20),
tRCD=self.ns(20),
tWR=self.ns(20),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) if not self.with_sdram:
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=13,
col_a=9
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(20),
tRCD=self.ns(20),
tWR=self.ns(20),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
default_subtarget = BaseSoC default_subtarget = BaseSoC

37
targets/kc705.py
View File

@ -80,25 +80,26 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)
sdram_geom = sdram.GeomSettings( if not self.with_sdram:
bank_a=3, sdram_geom = sdram.GeomSettings(
row_a=16, bank_a=3,
col_a=10 row_a=16,
) col_a=10
sdram_timing = sdram.TimingSettings( )
tRP=self.ns(15), sdram_timing = sdram.TimingSettings(
tRCD=self.ns(15), tRP=self.ns(15),
tWR=self.ns(15), tRCD=self.ns(15),
tWTR=2, tWR=self.ns(15),
tREFI=self.ns(7800, False), tWTR=2,
tRFC=self.ns(70), tREFI=self.ns(7800, False),
tRFC=self.ns(70),
req_queue_size=8, req_queue_size=8,
read_time=32, read_time=32,
write_time=16 write_time=16
) )
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3") self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
spiflash_pads = platform.request("spiflash") spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal() spiflash_pads.clk = Signal()

53
targets/mlabs_video.py
View File

@ -38,26 +38,35 @@ class BaseSoC(SDRAMSoC):
cpu_reset_address=0x00180000, cpu_reset_address=0x00180000,
**kwargs) **kwargs)
sdram_geom = sdram.GeomSettings( self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
bank_a=2,
row_a=13,
col_a=10
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),
req_queue_size=8, if not self.with_sdram:
read_time=32, sdram_geom = sdram.GeomSettings(
write_time=16 bank_a=2,
) row_a=13,
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", col_a=10
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") )
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"), self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
self.ns(110), self.ns(50)) self.ns(110), self.ns(50))
@ -67,11 +76,7 @@ class BaseSoC(SDRAMSoC):
if not self.with_rom: if not self.with_rom:
self.register_rom(self.norflash.bus) self.register_rom(self.norflash.bus)
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]
platform.add_platform_command(""" platform.add_platform_command("""
INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3"; INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";

53
targets/pipistrello.py
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@ -96,32 +96,33 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq) self.submodules.crg = _CRG(platform, clk_freq)
sdram_geom = sdram.GeomSettings( if not self.with_sdram:
bank_a=2, sdram_geom = sdram.GeomSettings(
row_a=13, bank_a=2,
col_a=10 row_a=13,
) col_a=10
sdram_timing = sdram.TimingSettings( )
tRP=self.ns(15), sdram_timing = sdram.TimingSettings(
tRCD=self.ns(15), tRP=self.ns(15),
tWR=self.ns(15), tRCD=self.ns(15),
tWTR=2, tWR=self.ns(15),
tREFI=self.ns(64*1000*1000/8192, False), tWTR=2,
tRFC=self.ns(72), tREFI=self.ns(64*1000*1000/8192, False),
req_queue_size=8, tRFC=self.ns(72),
read_time=32, req_queue_size=8,
write_time=16 read_time=32,
) write_time=16
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"), )
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1") self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"),
self.comb += [ "LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb), self.comb += [
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb), self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
] self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
platform.add_platform_command(""" ]
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; platform.add_platform_command("""
""") PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing) """)
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2) self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
self.flash_boot_address = 0x180000 self.flash_boot_address = 0x180000

37
targets/ppro.py
View File

@ -73,24 +73,25 @@ class BaseSoC(SDRAMSoC):
self.submodules.crg = _CRG(platform, clk_freq) self.submodules.crg = _CRG(platform, clk_freq)
sdram_geom = sdram.GeomSettings( if not self.with_sdram:
bank_a=2, sdram_geom = sdram.GeomSettings(
row_a=12, bank_a=2,
col_a=8 row_a=12,
) col_a=8
sdram_timing = sdram.TimingSettings( )
tRP=self.ns(15), sdram_timing = sdram.TimingSettings(
tRCD=self.ns(15), tRP=self.ns(15),
tWR=self.ns(14), tRCD=self.ns(15),
tWTR=2, tWR=self.ns(14),
tREFI=self.ns(64*1000*1000/4096, False), tWTR=2,
tRFC=self.ns(66), tREFI=self.ns(64*1000*1000/4096, False),
req_queue_size=8, tRFC=self.ns(66),
read_time=32, req_queue_size=8,
write_time=16 read_time=32,
) write_time=16
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram")) )
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing) self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6) self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000 self.flash_boot_address = 0x70000