targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)

misoclib/soc/sdram.py

@@ -70,6 +70,7 @@ class SDRAMSoC(SoC):
 				raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
 
 	def do_finalize(self):
+		if not self.with_sdram:
 			if not self._sdram_phy_registered:
 				raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
 		SoC.do_finalize(self)

targets/de0nano.py

@@ -87,6 +87,9 @@ class BaseSoC(SDRAMSoC):
 			with_rom=True,
 			**kwargs)
 
+		self.submodules.crg = _CRG(platform)
+
+		if not self.with_sdram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=2,
 				row_a=13,
@@ -106,8 +109,6 @@ class BaseSoC(SDRAMSoC):
 				write_time=16
 			)
 
-		self.submodules.crg = _CRG(platform)
-
 			self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
 			self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
 

targets/kc705.py

@@ -80,6 +80,7 @@ class BaseSoC(SDRAMSoC):
 
 		self.submodules.crg = _CRG(platform)
 
+		if not self.with_sdram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=3,
 				row_a=16,

targets/mlabs_video.py

@@ -38,6 +38,9 @@ class BaseSoC(SDRAMSoC):
 			cpu_reset_address=0x00180000,
 			**kwargs)
 
+		self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
+
+		if not self.with_sdram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=2,
 				row_a=13,
@@ -59,6 +62,12 @@ class BaseSoC(SDRAMSoC):
 				rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
 			self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
 
+
+			self.comb += [
+				self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
+				self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
+			]
+
 		self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
 			self.ns(110), self.ns(50))
 		self.flash_boot_address = 0x001a0000
@@ -67,11 +76,7 @@ class BaseSoC(SDRAMSoC):
 		if not self.with_rom:
 			self.register_rom(self.norflash.bus)
 
-		self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
-		self.comb += [
-			self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
-			self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
-		]
+
 		platform.add_platform_command("""
 INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";

targets/pipistrello.py

@@ -96,6 +96,7 @@ class BaseSoC(SDRAMSoC):
 
 		self.submodules.crg = _CRG(platform, clk_freq)
 
+		if not self.with_sdram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=2,
 				row_a=13,

targets/ppro.py

@@ -73,6 +73,7 @@ class BaseSoC(SDRAMSoC):
 
 		self.submodules.crg = _CRG(platform, clk_freq)
 
+		if not self.with_sdram:
 			sdram_geom = sdram.GeomSettings(
 				bank_a=2,
 				row_a=12,