cpu/zynq7000: enable software compilation

2022-01-19 02:47:18 +01:00 · 2022-01-19 02:47:18 +01:00 · 2bc1c3ac99
parent 682e4e0b7d
commit 2bc1c3ac99
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -935,7 +935,7 @@ class SoC(Module):
            self.mem_map.update(self.cpu.mem_map)

        # Add Bus Masters/CSR/IRQs.
-        if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)):
+        if not isinstance(self.cpu, cpu.CPUNone):
            if hasattr(self.cpu, "set_reset_address"):
                if reset_address is None:
                    reset_address = self.mem_map["rom"]