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build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen)

This commit is contained in:
Florent Kermarrec 2018-10-04 08:17:44 +02:00
parent 948527b0fe
commit 2be5205463
1 changed files with 4 additions and 3 deletions
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7
litex/build/xilinx/common.py
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@ -169,9 +169,9 @@ class XilinxDDROutputS7:
class XilinxDDRInputImplS7(Module): class XilinxDDRInputImplS7(Module):
def __init__(self, i, o1, o2, clk): def __init__(self, i, o1, o2, clk):
self.specials += Instance("IDDR", self.specials += Instance("IDDR",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", p_DDR_CLK_EDGE="SAME_EDGE",
i_C=clk, i_CE=1, i_S=0, i_R=0, i_C=clk, i_CE=1, i_S=0, i_R=0,
o_D=i, i_Q1=o1, i_Q2=o2, i_D=i, o_Q1=o1, o_Q2=o2,
) )
@ -206,9 +206,10 @@ class XilinxDDRInputImplKU(Module):
self.specials += Instance("IDDRE1", self.specials += Instance("IDDRE1",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
p_IS_C_INVERTED=0, p_IS_C_INVERTED=0,
p_IS_CB_INVERTED=1,
i_D=i, i_D=i,
o_Q1=o1, o_Q2=o2, o_Q1=o1, o_Q2=o2,
i_C=clk, i_CB=~clk, i_C=clk, i_CB=clk,
i_R=0 i_R=0
) )