build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen)
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948527b0fe
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2be5205463
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@ -169,9 +169,9 @@ class XilinxDDROutputS7:
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class XilinxDDRInputImplS7(Module):
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def __init__(self, i, o1, o2, clk):
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self.specials += Instance("IDDR",
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p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
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p_DDR_CLK_EDGE="SAME_EDGE",
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i_C=clk, i_CE=1, i_S=0, i_R=0,
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o_D=i, i_Q1=o1, i_Q2=o2,
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i_D=i, o_Q1=o1, o_Q2=o2,
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)
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@ -206,9 +206,10 @@ class XilinxDDRInputImplKU(Module):
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self.specials += Instance("IDDRE1",
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p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
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p_IS_C_INVERTED=0,
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p_IS_CB_INVERTED=1,
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i_D=i,
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o_Q1=o1, o_Q2=o2,
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i_C=clk, i_CB=~clk,
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i_C=clk, i_CB=clk,
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i_R=0
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)
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