soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore)
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@ -8,37 +8,14 @@ from migen import *
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from migen.genlib.record import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR
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from litex.soc.integration.soc_core import *
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from litedram.frontend.wishbone import *
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from litedram.frontend.axi import *
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from litedram import dfii, core
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from litedram.core import LiteDRAMCore
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__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
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# Controller Injector ------------------------------------------------------------------------------
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# FIXME: move to LiteDRAM
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class ControllerInjector(Module, AutoCSR):
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def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs):
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self.submodules.dfii = dfii.DFIInjector(
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geom_settings.addressbits,
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geom_settings.bankbits,
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phy.settings.nranks,
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phy.settings.dfi_databits,
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phy.settings.nphases)
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self.comb += self.dfii.master.connect(phy.dfi)
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self.submodules.controller = controller = core.LiteDRAMController(
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phy.settings, geom_settings, timing_settings,
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clk_freq, **kwargs)
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self.comb += controller.dfi.connect(self.dfii.slave)
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self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface)
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# SoCSDRAM -----------------------------------------------------------------------------------------
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class SoCSDRAM(SoCCore):
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@ -69,8 +46,12 @@ class SoCSDRAM(SoCCore):
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self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
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# LiteDRAM core ----------------------------------------------------------------------------
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self.submodules.sdram = ControllerInjector(
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phy, geom_settings, timing_settings, self.clk_freq, **kwargs)
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self.submodules.sdram = LiteDRAMCore(
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phy = phy,
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geom_settings = geom_settings,
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timing_settings = timing_settings,
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clk_freq = self.clk_freq,
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**kwargs)
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# SoC <--> L2 Cache <--> LiteDRAM ----------------------------------------------------------
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if self.with_wishbone:
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@ -107,8 +88,8 @@ class SoCSDRAM(SoCCore):
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# L2 Cache <--> LiteDRAM bridge --------------------------------------------------------
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if use_axi:
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axi_port = LiteDRAMAXIPort(
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port.data_width,
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port.address_width + log2_int(port.data_width//8))
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data_width = port.data_width,
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address_width = port.address_width + log2_int(port.data_width//8))
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axi2native = LiteDRAMAXI2Native(axi_port, port)
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self.submodules += axi2native
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self.submodules.wishbone_bridge = LiteDRAMWishbone2AXI(self.l2_cache.slave, axi_port)
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