mirror of
https://github.com/enjoy-digital/litex.git
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Merge pull request #175 from mithro/cpu-docs
Standardizing `cpu_variants` and adding lots of documentation
This commit is contained in:
enjoy-digital
GitHub
commit
2d5bae3def
11 changed files with 561 additions and 35 deletions
9
doc/BIOS.md
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9
doc/BIOS.md
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LiteX takes the philosophy of pushing as much onto the [[Soft CPU]] as possible. This means that most [[Gateware]] needs some accompanying code to initialize various settings and configurations. This specialized firmware is called the [[BIOS]].
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The [[BIOS]] generally does tasks like;
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* Train any external DDR memory
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* Load the user's [[Firmware]] into external memory via;
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* Communication channels like serial, tftp
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* Other storage systems like external flash.
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This can make it very fast to do development as you can iterate on [[Firmware]] development quickly.
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114
doc/Firmware.md
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114
doc/Firmware.md
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# Firmware
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LiteX is normally used with custom firmware running on the Soft-CPU inside the gateware (although in some cases it can be used with software running on a computer connected to the FPGA).
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This firmware can either be custom bare metal C code or be built on top of an existing real time operating system or even full operating system. All Soft-CPUs let you write your own bare metal firmware, but only some configurations work with operating systems.
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[Firmware which runs on LiteX Google Doc](https://docs.google.com/document/d/11uzjWRWk9-KuBFc7chUNUluL5ajysY2qfXvt1vttl7k/edit)
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# Baremetal
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## Support Soft-CPU Configurations
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**All** Soft-CPUs let you write your own bare metal firmware.
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* `lm32` (any variant)
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* `or1k` (any variant)
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* `vexriscv` (any variant)
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* `picorv32` (any variant)
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* `minerva` (any variant)
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---
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# MicroPython via [FuPy Project](https://fupy.github.io)
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From the FuPy website;
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> The aim of this project is to make MicroPython run on FPGAs using the LiteX & Migen+MiSoC technologies. This allows you to do full stack development (FPGA gateware & soft CPU firmware) in Python!
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## When to use?
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MicroPython is great to use when ease and speed of development is more important than performance. When coupled with LiteX you can push MicroPython even further by moving performance critical parts into FPGA gateware.
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## Hardware Requirements
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MicroPython is very light on requirements;
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* 32 kilobytes memory - can normally use internal block ram inside FPGA.
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* 128 kilobytes of storage - can normally use spare space in SPI flash used to configure the FPGA.
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## Support Soft-CPU Configurations
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* `lm32` (any variant), in FuPy repository
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* `or1k` (any variant), in FuPy repository
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* (in progress) `vexriscv` (any variant), in FuPy repository
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* (in progress) `picorv32` (any variant), in FuPy repository
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---
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# [NuttX](http://www.nuttx.org/)
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From the NuttX website;
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> NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 32-bit microcontroller environments, the primary governing standards in NuttX are Posix and ANSI standards. Additional standard APIs from Unix and other common RTOS's (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).
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## When to use?
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NuttX is a good option if you are already using NuttX or need to use a function that is already available in the NuttX ecosystem.
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## Hardware Requirements
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Unknown.
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LiteEth networking is supported.
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## Support Soft-CPU Configurations
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* `lm32` (any variant), in upstream repository
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---
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# [Zephyr](https://www.zephyrproject.org/)
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From the Zephyr website;
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> The Zephyr Project is a scalable real-time operating system (RTOS) supporting multiple hardware architectures, optimized for resource constrained devices, and built with safety and security in mind.
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## When to use?
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Zephyr is a great choice if you don't want to write your own bare metal firmware. It is under active development and moving forward quickly.
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It also has a coding style which makes it easy to move to Linux at a later state if you outgrow the abilities of Zephyr.
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## Hardware Requirements
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Zephyr is very light on requirements;
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* 32 kilobytes memory - can normally use internal block ram inside FPGA.
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* Some storage - can normally use spare space in SPI flash used to configure the FPGA.
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## Support Soft-CPU Configurations
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* `vexriscv` (any variant), in upstream repository
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* `picorv32` (any variant), out of tree port
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---
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# [Linux](https://en.wikipedia.org/wiki/Linux)
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From Wikipedia;
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> Linux is a family of free and open-source software operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991 by Linus Torvalds. ...
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> Linux also runs on embedded systems, i.e. devices whose operating system is typically built into the firmware and is highly tailored to the system. This includes routers, automation controls, televisions, digital video recorders, video game consoles, and smartwatches. Many smartphones and tablet computers run Android and other Linux derivatives.[30] Because of the dominance of Android on smartphones, Linux has the largest installed base of all general-purpose operating systems.
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## When to use?
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Linux tends to run quite slowly on the soft-CPUs supported by LiteX and needs hardware acceleration to do most useful operations. Linux makes the most sense were the existing large pool of Linux drivers or software is helpful.
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## Hardware Requirements
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Linux operating support generally needs;
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* Large and fast FPGA, something like Lattice ECP5 or Xilinx Artix 7 / Spartan 6.
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* 32+ megabytes memory, generally meaning external SDRAM or DDR RAM.
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* UART serial console.
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* Fast Ethernet (100 Megabit or 1 Gigabit Ethernet).
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* Some type of storage, large SPI flash or SD Card or SATA hard drives potential options.
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## Support Soft-CPU Configurations
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* `or1k` (`linux` variant), out of tree port being upstreamed
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* `vexriscv` (`linux` variant), out of tree port being upstreamed
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254
doc/Soft-CPU.md
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254
doc/Soft-CPU.md
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All LiteX SoCs need some type of CPU to operate correctly. Most use an "Soft CPU" embedded in the gateware for this purpose, but in some cases a host computer is used instead (for example this can be true in the PCIe card case).
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# Summary of Soft CPUs
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Currently the supported Soft CPUs are:
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* [`lm32`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/lm32) -- a [LatticeMico32](https://en.wikipedia.org/wiki/LatticeMico32) soft core.
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* [`or1k`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/mor1kx) -- an [OpenRISC 1000](https://openrisc.io/or1k.html) soft core (see also [Open RISC on Wikipedia](https://en.wikipedia.org/wiki/OpenRISC)).
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* [`picorv32`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/picorv32) -- a [Small RISC V core by Clifford Wolf](https://github.com/cliffordwolf/picorv32), implementing the `rv32imc` instruction set (or configured subsets)
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* [`vexriscv`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/vexriscv) -- an [FPGA Friendly RISC V core by SpinalHDL](https://github.com/SpinalHDL/VexRiscv), implementing the `rv32im` instruction set (hardware multiply optional)
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* [`minerva`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/minerva) -- an Minerva is a CPU core that currently implements the RISC-V RV32I instruction set and its microarchitecture is described in plain Python code using the [nMigen toolbox](https://github.com/m-labs/nmigen).
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# Soft CPU Variants
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Most of these CPUs have multiple configuration "variants" which customize the configuration to target a specific type of firmware and performance. All these CPUs can be used with your own bare metal firmware.
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## `minimal`
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Aliases: `min`
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Minimal is the smallest possible working configuration for a given CPU type. These features frequently disables a large number of useful such as illegal instruction exceptions and similar. It should only be used if the absolute smallest configuration is needed.
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### Supported CPUs
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* lm32
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* picorv32
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* vexriscv
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## `lite`
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**Aliases**: `zephyr`, `nuttx`, `light`
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Lite is the configuration which should work okay for bare metal firmware and RTOS like NuttX or Zephyr on small big FPGAs like the Lattice iCE40 parts. It can also be used for designs which are more resource constrained.
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### Recommended FPGAs
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* Lattice iCE40 Series - iCE40HX, iCE40LP, iCE40UP5K
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* Any resource constrained design.
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### Supported CPUs
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* lm32
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* vexriscv
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## `standard`
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**Aliases**: `std`
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Standard is the default configuration which should work well for bare metal firmware and RTOS like NuttX or Zephyr on modern big FPGAs.
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### Supported CPUs
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* lm32
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* minerva
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* picorv32
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* or1k
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* vexriscv
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### Recommended FPGAs
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* Xilinx Series 7 - Artix 7, Kintex 7, Spartan 7
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* Xilinx Spartan 6
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* Lattice ECP5
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## `linux`
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This target enables CPU features such as MMU that are required to get Linux booting.
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### Supported CPUs
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* or1k
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* vexriscv
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---
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# Soft CPU Extensions
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Extensions are added to the CPU variant with a `+`. For example a `minimal` variant with the `debug` extension would be `minimal+debug`.
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## `debug`
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The debug extension enables extra features useful for debugging. This normally includes things like JTAG port.
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### Supported CPUs
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* vexriscv
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## TODO - `mmu`
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The `mmu` extension enables a memory protection unit.
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### Supported CPUs
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* lm32 (untested)
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* vexriscv
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* or1k
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## TODO - `hmul`
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The `hmul` extension enables hardware multiplication acceleration.
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---
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# Binutils + Compiler
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* lm32 support was added to upstream GCC around ~2009, no clang support.
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* or1k support was added to upstream GCC in version 9.0.0, clang support was added upstream in version XXX
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* riscv support (VexRISCV, PicoRV32 and Minerva) was added to upstream GCC in version 7.1.0, clang support was added upstream in version 3.1
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You can compile your own compiler, download a precompiled toolchain or use an environment like [TimVideos LiteX BuildEnv](https://github.com/timvideos/litex-buildenv/) which provides precompiled toolchain for all three architectures.
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Note: RISC-V toolchains support or require various extensions. Generally `rv32i` is used on smaller FPGAs, and `rv32im` on larger FPGAs -- the `rv32im` adds hardware multiplication and division (see [RISC V ISA base and extensions on Wikipedia](https://en.wikipedia.org/wiki/RISC-V#ISA_base_and_extensions) for more detail).
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---
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# SoftCPU options
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## lm32 - [LatticeMico32](https://github.com/m-labs/lm32)
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[LatticeMico32](https://en.wikipedia.org/wiki/LatticeMico32) soft core, small and designed for an FPGA.
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### CPU Variants
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* minimal
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* lite
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* standard
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### Tooling support
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* Upstream GCC
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* Upstream Binutils
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### OS Support
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* No upstream Linux, very old Linux port
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* Upstream NuttX
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* No Zephyr support
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### Community
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* No current new activity
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|
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---
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|
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## [mor1k - OpenRISC](https://github.com/openrisc/mor1kx)
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An [OpenRISC 1000](https://openrisc.io/or1k.html) soft core (see also [Open RISC on Wikipedia](https://en.wikipedia.org/wiki/OpenRISC)).
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### CPU Variants
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* standard
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* linux
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### Tooling support
|
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* Upstream GCC
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* Upstream Binutils
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* Upstream clang
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### OS support
|
||||
|
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* No Zephyr support
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* No NuttX support
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* Upstream Linux
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### Community
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* Reasonable amount of activity.
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|
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---
|
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|
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## RISC-V - [VexRiscv](https://github.com/SpinalHDL/VexRiscv)
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A [FPGA Friendly RISC V core by SpinalHDL](https://github.com/SpinalHDL/VexRiscv), implementing the `rv32im` instruction set (hardware multiply optional).
|
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### CPU Variants
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* minimal
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* minimal_debug
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* lite
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* lite_debug
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* standard
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* standard_debug
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* linux
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|
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### Tooling support
|
||||
|
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* Upstream GCC
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* Upstream Binutils
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* Upstream clang
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|
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### OS support
|
||||
|
||||
* Upstream Zephyr
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* Unknown NuttX support
|
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* Upstream Linux (in progress)
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|
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### Community
|
||||
|
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* Lots of current activity
|
||||
* Currently supported under both LiteX & MiSoC
|
||||
|
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## RISC-V - [picorv32](https://github.com/cliffordwolf/picorv32/)
|
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|
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A [small RISC V core by Clifford Wolf](https://github.com/cliffordwolf/picorv32), implementing the `rv32imc` instruction set (or configured subsets).
|
||||
|
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### CPU Variants
|
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|
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* minimal
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* standard
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||||
|
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### Tooling support
|
||||
|
||||
* Upstream GCC
|
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* Upstream Binutils
|
||||
* Upstream clang
|
||||
|
||||
### OS support
|
||||
|
||||
* Out of tree Zephyr
|
||||
* Unknown NuttX support
|
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* Too small for Linux
|
||||
|
||||
### Community
|
||||
|
||||
* Some activity
|
||||
|
||||
## RISC-V - [`minerva`](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/minerva)
|
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|
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The Minerva is a CPU core that currently implements the RISC-V RV32I instruction set and its microarchitecture is described in plain Python code using the [nMigen toolbox](https://github.com/m-labs/nmigen).
|
||||
|
||||
### CPU Variants
|
||||
|
||||
* standard
|
||||
|
||||
### Tooling support
|
||||
|
||||
* Upstream GCC
|
||||
* Upstream Binutils
|
||||
* Upstream clang
|
||||
|
||||
### OS support
|
||||
|
||||
* Unknown Zephyr support
|
||||
* Unknown NuttX support
|
||||
* Unknown Linux support
|
||||
|
||||
### Community
|
||||
|
||||
* Some activity
|
||||
14
doc/pull-docs-from-buildenv-wiki.sh
Executable file
14
doc/pull-docs-from-buildenv-wiki.sh
Executable file
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@ -0,0 +1,14 @@
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#!/bin/bash
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# Soft-CPU - Description about supported Soft-CPUs.
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# BIOS - Information about the BIOS and what it is used for.
|
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# Firmware - Information about compatible Firmware.
|
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|
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for page in Soft-CPU BIOS Firmware; do
|
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curl https://raw.githubusercontent.com/wiki/timvideos/litex-buildenv/${page}.md > ${page}.md
|
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git add ${page}.md
|
||||
done
|
||||
|
||||
GIT_MSG=$(tempfile) || exit
|
||||
trap "rm -f -- '$GIT_MSG'" EXIT
|
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git commit --message "Updating documents from LiteX BuildEnv Wiki"
|
||||
|
|
@ -12,8 +12,8 @@ class LM32(Module):
|
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gcc_flags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled"
|
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linker_output_format = "elf32-lm32"
|
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|
||||
def __init__(self, platform, eba_reset, variant=None):
|
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assert variant in (None, "lite", "minimal"), "Unsupported variant %s" % variant
|
||||
def __init__(self, platform, eba_reset, variant="standard"):
|
||||
assert variant in ("standard", "lite", "minimal"), "Unsupported variant %s" % variant
|
||||
self.reset = Signal()
|
||||
self.ibus = i = wishbone.Interface()
|
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self.dbus = d = wishbone.Interface()
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|
|
@ -66,7 +66,7 @@ class LM32(Module):
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|||
self.add_sources(platform, variant)
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|
||||
@staticmethod
|
||||
def add_sources(platform, variant=None):
|
||||
def add_sources(platform, variant):
|
||||
vdir = os.path.join(
|
||||
os.path.abspath(os.path.dirname(__file__)), "verilog")
|
||||
platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
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|
|
@ -93,5 +93,7 @@ class LM32(Module):
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|||
platform.add_verilog_include_path(os.path.join(vdir, "config_minimal"))
|
||||
elif variant == "lite":
|
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platform.add_verilog_include_path(os.path.join(vdir, "config_lite"))
|
||||
else:
|
||||
elif variant == "standard":
|
||||
platform.add_verilog_include_path(os.path.join(vdir, "config"))
|
||||
else:
|
||||
raise TypeError("Unknown variant {}".format(variant))
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@ class Minerva(Module):
|
|||
gcc_flags = "-D__minerva__ -march=rv32i -mabi=ilp32"
|
||||
linker_output_format = "elf32-littleriscv"
|
||||
|
||||
def __init__(self, platform, cpu_reset_address, variant=None):
|
||||
assert variant is None, "Unsupported variant %s" % variant
|
||||
def __init__(self, platform, cpu_reset_address, variant="standard"):
|
||||
assert variant is "standard", "Unsupported variant %s" % variant
|
||||
self.reset = Signal()
|
||||
self.ibus = wishbone.Interface()
|
||||
self.dbus = wishbone.Interface()
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
#!/usr/bin/env python3
|
||||
import os
|
||||
|
||||
from migen import *
|
||||
|
|
@ -12,8 +13,8 @@ class MOR1KX(Module):
|
|||
gcc_flags = "-mhard-mul -mhard-div -mror"
|
||||
linker_output_format = "elf32-or1k"
|
||||
|
||||
def __init__(self, platform, reset_pc, variant=None):
|
||||
assert variant in (None, "linux"), "Unsupported variant %s" % variant
|
||||
def __init__(self, platform, reset_pc, variant="standard"):
|
||||
assert variant in ("standard", "linux"), "Unsupported variant %s" % variant
|
||||
self.reset = Signal()
|
||||
self.ibus = i = wishbone.Interface()
|
||||
self.dbus = d = wishbone.Interface()
|
||||
|
|
@ -47,7 +48,7 @@ class MOR1KX(Module):
|
|||
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
|
||||
)
|
||||
|
||||
if variant == None:
|
||||
if variant == "standard":
|
||||
# Use the default configuration
|
||||
pass
|
||||
elif variant == "linux":
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
#!/usr/bin/env python3
|
||||
import os
|
||||
|
||||
from migen import *
|
||||
|
|
@ -12,7 +13,7 @@ class PicoRV32(Module):
|
|||
gcc_flags_template = "-D__picorv32__ -mno-save-restore -march=rv32{ext} -mabi=ilp32"
|
||||
linker_output_format = "elf32-littleriscv"
|
||||
|
||||
def __init__(self, platform, progaddr_reset, variant):
|
||||
def __init__(self, platform, progaddr_reset, variant="standard"):
|
||||
self.gcc_flags = ""
|
||||
|
||||
self.reset = Signal()
|
||||
|
|
@ -61,7 +62,7 @@ class PicoRV32(Module):
|
|||
"p_STACKADDR" : 0xffffffff
|
||||
}
|
||||
|
||||
if variant == None:
|
||||
if variant == "standard":
|
||||
self.gcc_flags = PicoRV32.gcc_flags_template.format(ext="im")
|
||||
elif variant == "minimal":
|
||||
picorv32_params.update({
|
||||
|
|
|
|||
|
|
@ -6,18 +6,51 @@ from litex.soc.interconnect import wishbone
|
|||
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
|
||||
|
||||
|
||||
CPU_VARIANTS = {
|
||||
"minimal": "VexRiscv_Min",
|
||||
"minimal+debug": "VexRiscv_MinDebug",
|
||||
"lite": "VexRiscv_Lite",
|
||||
"lite+debug": "VexRiscv_LiteDebug",
|
||||
"standard": "VexRiscv",
|
||||
"standard+debug": "VexRiscv_Debug",
|
||||
"full": "VexRiscv_Full",
|
||||
"full+debug": "VexRiscv_FullDebug",
|
||||
"linux": "VexRiscv_Linux",
|
||||
}
|
||||
|
||||
|
||||
GCC_FLAGS = {
|
||||
# /-------- Base ISA
|
||||
# |/------- Hardware Multiply + Divide
|
||||
# ||/----- Atomics
|
||||
# |||/---- Compressed ISA
|
||||
# ||||/--- Single-Precision Floating-Point
|
||||
# |||||/-- Double-Precision Floating-Point
|
||||
# imacfd
|
||||
"minimal": "-march=rv32i -mabi=ilp32",
|
||||
"minimal+debug": "-march=rv32i -mabi=ilp32",
|
||||
"lite": "-march=rv32i -mabi=ilp32",
|
||||
"lite+debug": "-march=rv32i -mabi=ilp32",
|
||||
"standard": "-march=rv32im -mabi=ilp32",
|
||||
"standard+debug": "-march=rv32im -mabi=ilp32",
|
||||
# Does full have floating point? - Add -march=fd, and -mabi=fd
|
||||
"full": "-march=rv32imac -mabi=ilp32",
|
||||
"full+debug": "-march=rv32imac -mabi=ilp32",
|
||||
"linux": "-march=rv32imac -mabi=ilp32",
|
||||
}
|
||||
|
||||
|
||||
class VexRiscv(Module, AutoCSR):
|
||||
name = "vexriscv"
|
||||
endianness = "little"
|
||||
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf")
|
||||
gcc_flags = "-D__vexriscv__ -march=rv32im -mabi=ilp32"
|
||||
linker_output_format = "elf32-littleriscv"
|
||||
|
||||
def __init__(self, platform, cpu_reset_address, variant=None):
|
||||
variant = "std" if variant is None else variant
|
||||
variant = "std_debug" if variant == "debug" else variant
|
||||
variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug", "full", "full_debug")
|
||||
assert variant in variants, "Unsupported variant %s" % variant
|
||||
def __init__(self, platform, cpu_reset_address, variant="standard"):
|
||||
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
|
||||
|
||||
self.gcc_flags = GCC_FLAGS[variant]
|
||||
|
||||
self.platform = platform
|
||||
self.variant = variant
|
||||
self.external_variant = None
|
||||
|
|
@ -150,18 +183,8 @@ class VexRiscv(Module, AutoCSR):
|
|||
)
|
||||
|
||||
@staticmethod
|
||||
def add_sources(platform, variant="std"):
|
||||
verilog_variants = {
|
||||
"std": "VexRiscv.v",
|
||||
"std_debug": "VexRiscv_Debug.v",
|
||||
"lite": "VexRiscv_Lite.v",
|
||||
"lite_debug": "VexRiscv_LiteDebug.v",
|
||||
"min": "VexRiscv_Min.v",
|
||||
"min_debug": "VexRiscv_MinDebug.v",
|
||||
"full": "VexRiscv_Full.v",
|
||||
"full_debug": "VexRiscv_FullDebug.v",
|
||||
}
|
||||
cpu_filename = verilog_variants[variant]
|
||||
def add_sources(platform, variant="standard"):
|
||||
cpu_filename = CPU_VARIANTS[variant]
|
||||
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
|
||||
platform.add_source(os.path.join(vdir, cpu_filename))
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
#!/usr/bin/env python3
|
||||
import os
|
||||
import struct
|
||||
import inspect
|
||||
|
|
@ -23,6 +24,42 @@ __all__ = [
|
|||
]
|
||||
|
||||
|
||||
CPU_VARIANTS = {
|
||||
# "official name": ["alias 1", "alias 2"],
|
||||
"minimal" : ["min",],
|
||||
"lite" : ["light", "zephyr", "nuttx"],
|
||||
"standard": [None, "std"],
|
||||
"full": [],
|
||||
"linux" : [],
|
||||
}
|
||||
CPU_VARIANTS_EXTENSIONS = ["debug"]
|
||||
|
||||
|
||||
class InvalidCPUVariantError(ValueError):
|
||||
def __init__(self, variant):
|
||||
msg = """\
|
||||
Invalid cpu_variant value: {}
|
||||
|
||||
Possible Values:
|
||||
""".format(variant)
|
||||
for k, v in CPU_VARIANTS.items():
|
||||
msg += " - {} (aliases: {})\n".format(k, ", ".join(str(s) for s in v))
|
||||
ValueError.__init__(self, msg)
|
||||
|
||||
|
||||
class InvalidCPUExtensionError(ValueError):
|
||||
def __init__(self, variant):
|
||||
msg = """\
|
||||
Invalid extension in cpu_variant value: {}
|
||||
|
||||
Possible Values:
|
||||
""".format(variant)
|
||||
for e in CPU_VARIANTS_EXTENSIONS:
|
||||
msg += " - {}\n".format(e)
|
||||
ValueError.__init__(self, msg)
|
||||
|
||||
|
||||
|
||||
def version(with_time=True):
|
||||
import datetime
|
||||
import time
|
||||
|
|
@ -77,6 +114,7 @@ def get_mem_data(filename, endianness="big", mem_size=None):
|
|||
i += 1
|
||||
return data
|
||||
|
||||
|
||||
class ReadOnlyDict(dict):
|
||||
def __readonly__(self, *args, **kwargs):
|
||||
raise RuntimeError("Cannot modify ReadOnlyDict")
|
||||
|
|
@ -162,7 +200,27 @@ class SoCCore(Module):
|
|||
if cpu_type == "None":
|
||||
cpu_type = None
|
||||
self.cpu_type = cpu_type
|
||||
self.cpu_variant = cpu_variant
|
||||
|
||||
# Support the old style which used underscore for separator
|
||||
if cpu_variant is None:
|
||||
cpu_variant = "standard"
|
||||
cpu_variant = cpu_variant.replace('_', '+')
|
||||
# Check for valid CPU variants.
|
||||
cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+')
|
||||
for key, values in CPU_VARIANTS.items():
|
||||
if cpu_variant_processor not in [key,]+values:
|
||||
continue
|
||||
self.cpu_variant = key
|
||||
break
|
||||
else:
|
||||
raise InvalidCPUVariantError(cpu_variant)
|
||||
|
||||
# Check for valid CPU extensions.
|
||||
for ext in sorted(cpu_variant_ext):
|
||||
if ext not in CPU_VARIANTS_EXTENSIONS:
|
||||
raise InvalidCPUExtensionError(cpu_variant)
|
||||
self.cpu_variant += "+"+ext
|
||||
|
||||
if integrated_rom_size:
|
||||
cpu_reset_address = self.mem_map["rom"]
|
||||
self.cpu_reset_address = cpu_reset_address
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
import subprocess
|
||||
import unittest
|
||||
import os
|
||||
|
||||
|
|
@ -6,6 +7,9 @@ from migen import *
|
|||
from litex.soc.integration.builder import *
|
||||
|
||||
|
||||
RUNNING_ON_TRAVIS = (os.getenv('TRAVIS', 'false').lower() == 'true')
|
||||
|
||||
|
||||
def build_test(socs):
|
||||
errors = 0
|
||||
for soc in socs:
|
||||
|
|
@ -98,8 +102,54 @@ class TestTargets(unittest.TestCase):
|
|||
platforms += ["avalanche"] # PolarFire
|
||||
|
||||
for p in platforms:
|
||||
os.system("litex/boards/targets/simple.py litex.boards.platforms." + p +
|
||||
" --cpu-type=vexriscv " +
|
||||
" --no-compile-software " +
|
||||
" --no-compile-gateware " +
|
||||
" --uart-stub=True")
|
||||
with self.subTest(platform=p):
|
||||
cmd = """\
|
||||
litex/boards/targets/simple.py litex.boards.platforms.{p} \
|
||||
--cpu-type=vexriscv \
|
||||
--no-compile-software \
|
||||
--no-compile-gateware \
|
||||
--uart-stub=True \
|
||||
""".format(p=p)
|
||||
subprocess.check_call(cmd, shell=True)
|
||||
|
||||
def run_variants(self, cpu, variants):
|
||||
for v in variants:
|
||||
with self.subTest(cpu=cpu, variant=v):
|
||||
self.run_variant(cpu, v)
|
||||
|
||||
def run_variant(self, cpu, variant):
|
||||
cmd = """\
|
||||
litex/boards/targets/simple.py litex.boards.platforms.arty \
|
||||
--cpu-type={c} \
|
||||
--cpu-variant={v} \
|
||||
--no-compile-software \
|
||||
--no-compile-gateware \
|
||||
--uart-stub=True \
|
||||
""".format(c=cpu, v=variant)
|
||||
subprocess.check_output(cmd, shell=True)
|
||||
|
||||
# Build some variants for the arty platform to make sure they work.
|
||||
def test_variants_riscv(self):
|
||||
cpu_variants = {
|
||||
'picorv32': ('standard', 'minimal'),
|
||||
'vexriscv': ('standard', 'minimal', 'lite', 'lite+debug', 'full+debug'),
|
||||
'minerva': ('standard',),
|
||||
}
|
||||
for cpu, variants in cpu_variants.items():
|
||||
self.run_variants(cpu, variants)
|
||||
|
||||
def test_bad_variants(self):
|
||||
with self.assertRaises(subprocess.CalledProcessError):
|
||||
self.run_variant('vexriscv', 'bad')
|
||||
|
||||
def test_bad_variant_extension(self):
|
||||
with self.assertRaises(subprocess.CalledProcessError):
|
||||
self.run_variant('vexriscv', 'standard+bad')
|
||||
|
||||
@unittest.skipIf(RUNNING_ON_TRAVIS, "No lm32 toolchain on Travis-CI")
|
||||
def test_variants_lm32(self):
|
||||
self.run_variants('lm32', ('standard', 'minimal', 'lite'))
|
||||
|
||||
@unittest.skipIf(RUNNING_ON_TRAVIS, "No or1k toolchain on Travis-CI")
|
||||
def test_variants_or1k(self):
|
||||
self.run_variants('or1k', ('standard', 'linux'))
|
||||
|
|
|
|||
Loading…
Reference in a new issue