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fhdl/verilog: sort clock domains by name

This commit is contained in:
Sebastien Bourdeauducq 2012-09-11 10:00:03 +02:00
parent 9a18a9df3f
commit 2e14569b5c
1 changed files with 2 additions and 1 deletions
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3
migen/fhdl/verilog.py
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@ -1,4 +1,5 @@
from functools import partial from functools import partial
from operator import itemgetter
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.fhdl.structure import _Operator, _Slice, _Assign from migen.fhdl.structure import _Operator, _Slice, _Assign
@ -171,7 +172,7 @@ def _printcomb(f, ns, display_run):
def _printsync(f, ns, clock_domains): def _printsync(f, ns, clock_domains):
r = "" r = ""
for k, v in f.sync.items(): for k, v in sorted(f.sync.items(), key=itemgetter(0)):
r += "always @(posedge " + ns.get_name(clock_domains[k].clk) + ") begin\n" r += "always @(posedge " + ns.get_name(clock_domains[k].clk) + ") begin\n"
r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(clock_domains[k].rst, v)) r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(clock_domains[k].rst, v))
r += "end\n\n" r += "end\n\n"