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Fix vexii axi3

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This commit is contained in:
Dolu1990 2024-06-12 19:33:20 +02:00
parent 8bb10e1617
commit 2e4813d6ae
1 changed files with 5 additions and 0 deletions
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5
litex/soc/cores/cpu/vexiiriscv/core.py
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@ -534,6 +534,11 @@ class VexiiRiscv(CPU):
i_mBus_rlast = mbus.r.last,
)
if VexiiRiscv.with_axi3:
self.cpu_params.update(
o_mBus_wid=mbus.w.id
)
def do_finalize(self):
assert hasattr(self, "reset_address")