Fix vexii axi3

2024-06-12 19:33:20 +02:00 · 2024-06-12 19:33:20 +02:00 · 2e4813d6ae
parent 8bb10e1617
commit 2e4813d6ae
1 changed files with 5 additions and 0 deletions
--- a/litex/soc/cores/cpu/vexiiriscv/core.py
+++ b/litex/soc/cores/cpu/vexiiriscv/core.py
@ -534,6 +534,11 @@ class VexiiRiscv(CPU):
            i_mBus_rlast     = mbus.r.last,
        )

+        if VexiiRiscv.with_axi3:
+            self.cpu_params.update(
+                o_mBus_wid=mbus.w.id
+            )
+
    def do_finalize(self):
        assert hasattr(self, "reset_address")