Fix vexii axi3
This commit is contained in:
parent
8bb10e1617
commit
2e4813d6ae
|
@ -534,6 +534,11 @@ class VexiiRiscv(CPU):
|
|||
i_mBus_rlast = mbus.r.last,
|
||||
)
|
||||
|
||||
if VexiiRiscv.with_axi3:
|
||||
self.cpu_params.update(
|
||||
o_mBus_wid=mbus.w.id
|
||||
)
|
||||
|
||||
def do_finalize(self):
|
||||
assert hasattr(self, "reset_address")
|
||||
|
||||
|
|
Loading…
Reference in New Issue