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migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb)

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Florent Kermarrec 2015-03-18 14:41:43 +01:00
parent bdc47b205a
commit 2fc2f8a6c0
1 changed files with 1 additions and 1 deletions
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2
migen/genlib/io.py
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@ -35,7 +35,7 @@ class DifferentialOutput(Special):
raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
class CRG(Module):
def __init__(self, clk, rst=Signal()):
def __init__(self, clk, rst=0):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)