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Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)"

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This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e453.
This commit is contained in:
Sebastien Bourdeauducq 2015-03-18 12:08:25 +01:00
parent 89fefef3f8
commit bdc47b205a
1 changed files with 3 additions and 11 deletions
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14
migen/fhdl/verilog.py
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@ -279,19 +279,11 @@ def _printinit(f, ios, ns):
- ios \
- list_targets(f) \
- list_special_ios(f, False, True, True)
wires = (_list_comb_wires(f) | list_special_ios(f, True, False, False)) \
- ios \
- list_targets(f) \
- list_special_ios(f, False, True, True)
if signals:
r += "initial begin\n"
for s in sorted(signals, key=lambda x: x.huid):
if s in wires:
r += "assign" + ns.get_name(s) + " = " + _printexpr(ns, s.reset)[0] + ";\n"
r += "always @(*) begin\n"
for s in sorted(signals, key=lambda x: x.huid):
if s not in wires:
r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
r += "end\n"
r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
r += "end\n\n"
return r
def convert(f, ios=None, name="top",