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fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)

This commit is contained in:
Florent Kermarrec 2015-03-16 23:39:32 +01:00
parent b5a9909b08
commit e946f6e453
1 changed files with 11 additions and 3 deletions
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14
migen/fhdl/verilog.py
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@ -276,11 +276,19 @@ def _printinit(f, ios, ns):
- ios \
- list_targets(f) \
- list_special_ios(f, False, True, True)
wires = (_list_comb_wires(f) | list_special_ios(f, True, False, False)) \
- ios \
- list_targets(f) \
- list_special_ios(f, False, True, True)
if signals:
r += "initial begin\n"
for s in sorted(signals, key=lambda x: x.huid):
r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
r += "end\n\n"
if s in wires:
r += "assign" + ns.get_name(s) + " = " + _printexpr(ns, s.reset)[0] + ";\n"
r += "always @(*) begin\n"
for s in sorted(signals, key=lambda x: x.huid):
if s not in wires:
r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
r += "end\n"
return r
def convert(f, ios=None, name="top",