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fhdl/verilog: Fix regression introduced in to_signed function.

This commit is contained in:
Florent Kermarrec 2021-10-15 21:46:42 +02:00
parent 942d3165bd
commit 306bdcaed8
1 changed files with 1 additions and 1 deletions
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litex/gen/fhdl/verilog.py
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@ -117,7 +117,7 @@ def _print_operator(ns, node):
assert arity in [UNARY, BINARY, TERNARY] assert arity in [UNARY, BINARY, TERNARY]
def to_signed(r): def to_signed(r):
return f"$signed({{1'd0 {r}}}))" return f"$signed({{1'd0, {r}}})"
# Unary Operator. # Unary Operator.
if arity == UNARY: if arity == UNARY: