build/xilinx/ise: Fix Yosys flow
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5796f30b18
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30a7a1cf16
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@ -44,13 +44,12 @@ class XilinxISEToolchain(GenericToolchain):
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self.bitgen_opt = "-g Binary:Yes -w"
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self.bitgen_opt = "-g Binary:Yes -w"
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self.ise_commands = ""
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self.ise_commands = ""
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self.mode = "xst"
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self.mode = "xst"
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self.isemode = "xst"
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self._isemode = "xst"
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def build(self, platform, fragment,
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def build(self, platform, fragment,
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mode = "xst",
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mode = "xst",
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**kwargs):
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**kwargs):
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self.mode = mode
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self._mode = mode
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self._isemode = mode if mode in ["xst", "cpld"] else "edif"
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self._isemode = mode if mode in ["xst", "cpld"] else "edif"
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return GenericToolchain.build(self, platform, fragment, **kwargs)
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return GenericToolchain.build(self, platform, fragment, **kwargs)
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@ -118,11 +117,11 @@ class XilinxISEToolchain(GenericToolchain):
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# Yosys Run ----------------------------------------------------------------------------------------
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# Yosys Run ----------------------------------------------------------------------------------------
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def _run_yosys(build_name):
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def _run_yosys(self):
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device = self.platform.device
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device = self.platform.device
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ys_contents = ""
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ys_contents = ""
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incflags = ""
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incflags = ""
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for path in platform.verilog_include_paths:
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for path in self.platform.verilog_include_paths:
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incflags += " -I" + path
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incflags += " -I" + path
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for filename, language, library, *copy in self.platform.sources:
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for filename, language, library, *copy in self.platform.sources:
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ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
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ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
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