Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

versa_ecp5: Remove negative diff IO pins 

In Lattice FPGAs only the positive side of differential pairs should
be specified (unlike Xilinx)

These are a warning on Diamond (which trims unused IO) and an error
with Yosys/nextpnr (which doesn't so they conflict when the positive
pin is 'expanded').

Already this is the case for the clock input, this commit performs
the same change for the DDR3 pins.
This commit is contained in:
David Shah 2019-02-22 12:12:10 +00:00
parent c03b1ad13a
commit 321dd8fcf6
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/boards/platforms/versa_ecp5.py
View File

@ -50,9 +50,7 @@ _io = [
IOStandard("SSTL135_I"),
Misc("TERMINATION=75")),
Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
Subsignal("dqs_n", Pins("J1 G5"), IOStandard("SSTL135D_I")),
Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")),
Subsignal("clk_n", Pins("N5"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),