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soc/sdram: sync with new mibuild toolchain management

This commit is contained in:
Sebastien Bourdeauducq 2015-03-13 23:19:08 +01:00
parent c3c7f627d9
commit 32676fffd2
1 changed files with 2 additions and 2 deletions
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4
misoclib/soc/sdram.py
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@ -53,8 +53,8 @@ class SDRAMSoC(SoC):
# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache. # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.1?). # Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
# Remove this workaround when fixed by Xilinx. # Remove this workaround when fixed by Xilinx.
from mibuild.xilinx.vivado import XilinxVivadoPlatform from mibuild.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform, XilinxVivadoPlatform): if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())) self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
else: else: