soc/interconnect/axi: improve Timeout module and test it with shared interconnect
This commit is contained in:
Jędrzej Boczar
parent
2cab7fbf0f
commit
32d9e212c5
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@ -893,31 +893,36 @@ class AXILiteTimeout(Module):
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"""Protect master against slave timeouts (master _has_ to respond correctly)"""
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def __init__(self, master, cycles):
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self.error = Signal()
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wr_error = Signal()
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rd_error = Signal()
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# # #
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timer = WaitTimer(int(cycles))
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self.submodules += timer
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is_write = Signal()
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is_read = Signal()
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self.comb += self.error.eq(wr_error | rd_error)
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self.submodules.fsm = fsm = FSM()
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wr_timer = WaitTimer(int(cycles))
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rd_timer = WaitTimer(int(cycles))
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self.submodules += wr_timer, rd_timer
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def channel_fsm(timer, wait_cond, error, response):
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fsm = FSM(reset_state="WAIT")
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fsm.act("WAIT",
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is_write.eq((master.aw.valid & ~master.aw.ready) | (master.w.valid & ~master.w.ready)),
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is_read.eq(master.ar.valid & ~master.ar.ready),
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timer.wait.eq(is_write | is_read),
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timer.wait.eq(wait_cond),
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# done is updated in `sync`, so we must make sure that `ready` has not been issued
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# by slave during that single cycle, by checking `timer.wait`
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If(timer.done & timer.wait,
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self.error.eq(1),
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If(is_write,
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NextState("RESPOND-WRITE")
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).Else(
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NextState("RESPOND-READ")
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error.eq(1),
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NextState("RESPOND")
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)
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)
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)
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fsm.act("RESPOND-WRITE",
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fsm.act("RESPOND", *response)
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return fsm
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self.submodules.wr_fsm = channel_fsm(
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timer = wr_timer,
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wait_cond = (master.aw.valid & ~master.aw.ready) | (master.w.valid & ~master.w.ready),
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error = wr_error,
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response = [
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master.aw.ready.eq(master.aw.valid),
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master.w.ready.eq(master.w.valid),
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master.b.valid.eq(~master.aw.valid & ~master.w.valid),
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@ -925,8 +930,13 @@ class AXILiteTimeout(Module):
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If(master.b.valid & master.b.ready,
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NextState("WAIT")
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)
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)
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fsm.act("RESPOND-READ",
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])
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self.submodules.rd_fsm = channel_fsm(
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timer = rd_timer,
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wait_cond = master.ar.valid & ~master.ar.ready,
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error = rd_error,
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response = [
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master.ar.ready.eq(master.ar.valid),
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master.r.valid.eq(~master.ar.valid),
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master.r.resp.eq(RESP_SLVERR),
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@ -934,7 +944,7 @@ class AXILiteTimeout(Module):
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If(master.r.valid & master.r.ready,
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NextState("WAIT")
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)
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)
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])
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# AXILite Interconnect -----------------------------------------------------------------------------
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@ -1051,8 +1061,6 @@ class AXILiteDecoder(Module):
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slave_sel = new_slave_sel()
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# we need to hold the slave selected until all responses come back
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# TODO: check if this will break Timeout if a slave does not respond?
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# should probably work correctly as it uses master signals
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# TODO: we could reuse arbiter counters
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locks = {
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"write": AXILiteRequestCounter(
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@ -974,10 +974,12 @@ class TestAXILiteInterconnect(unittest.TestCase):
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def interconnect_shared_test(self, master_patterns, slave_decoders,
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master_delay=0, slave_ready_latency=0, slave_response_latency=0,
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timeout=300, **kwargs):
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disconnected_slaves=None, timeout=300, **kwargs):
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# number of masters/slaves is defined by the number of patterns/decoders
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# master_patterns: list of patterns per master, pattern = list(tuple(rw, addr, data))
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# slave_decoders: list of address decoders per slave
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# delay/latency: control the speed of masters/slaves
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# disconnected_slaves: list of slave numbers that shouldn't respond to any transactions
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class DUT(Module):
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def __init__(self, n_masters, decoders, **kwargs):
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self.masters = [AXILiteInterface(name="master") for _ in range(n_masters)]
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@ -1013,9 +1015,11 @@ class TestAXILiteInterconnect(unittest.TestCase):
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# run simulator
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generators = [gen.handler() for gen in pattern_generators]
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generators += [checker.handler(slave) for (slave, checker) in zip(dut.slaves, checkers)]
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generators += [checker.handler(slave)
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for i, (slave, checker) in enumerate(zip(dut.slaves, checkers))
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if i not in (disconnected_slaves or [])]
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generators += [timeout_generator(timeout)]
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run_simulation(dut, generators)
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run_simulation(dut, generators, vcd_name='sim.vcd')
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return pattern_generators, checkers
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@ -1075,7 +1079,10 @@ class TestAXILiteInterconnect(unittest.TestCase):
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read_errors = [" 0x{:08x} vs 0x{:08x}".format(v, ref) for v, ref in gen.read_errors]
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msg = "\ngen.resp_errors = {}\ngen.read_errors = \n{}".format(
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gen.resp_errors, "\n".join(read_errors))
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if not kwargs.get("disconnected_slaves", None):
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self.assertEqual(gen.errors, 0, msg=msg)
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else: # when some slaves are disconnected we should have some errors
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self.assertNotEqual(gen.errors, 0, msg=msg)
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# make sure all the accesses at slave side are in correct address region
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for i_slave, (checker, decoder) in enumerate(zip(checkers, slave_decoders_py)):
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@ -1104,3 +1111,8 @@ class TestAXILiteInterconnect(unittest.TestCase):
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master_delay=rand,
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slave_ready_latency=rand,
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slave_response_latency=rand)
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def test_interconnect_shared_stress_timeout(self):
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self.interconnect_shared_stress_test(timeout=4000,
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disconnected_slaves=[1],
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timeout_cycles=50)
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