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litex/soc: support model-version of GMII PHY in add_ether{net,bone}

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This not only tests for the precise PHY model, but also whether there
is a model attribute in the ethphy instance and whether that is set to
True.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
This commit is contained in:
Leon Schuermann 2021-09-01 20:42:23 +02:00
parent 2852e80eae
commit 339fabf615
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc.py
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@ -1433,7 +1433,7 @@ class LiteXSoC(SoC):
# Timing constraints # Timing constraints
eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel): if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq) self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
@ -1485,7 +1485,7 @@ class LiteXSoC(SoC):
# Timing constraints # Timing constraints
eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel): if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq) self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)