Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

top: connect UART IRQ

This commit is contained in:
Sebastien Bourdeauducq 2012-02-06 17:45:40 +01:00
parent 5dc875de69
commit 33f1c456bf
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
top.py
View File

@ -39,7 +39,11 @@ def get():
uart0 = uart.UART(0, clk_freq, baud=115200) uart0 = uart.UART(0, clk_freq, baud=115200)
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface]) csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
frag = autofragment.from_local() interrupts = Fragment([
cpu0.interrupt[0].eq(uart0.events.irq)
])
frag = autofragment.from_local() + interrupts
src_verilog, vns = verilog.convert(frag, src_verilog, vns = verilog.convert(frag,
{clkfx_sys.clkin, reset0.trigger_reset}, {clkfx_sys.clkin, reset0.trigger_reset},
name="soc", name="soc",