top: connect UART IRQ

2012-02-06 17:45:40 +01:00 · 2012-02-06 17:45:40 +01:00 · 33f1c456bf
parent 5dc875de69
commit 33f1c456bf
1 changed files with 5 additions and 1 deletions
--- a/top.py
+++ b/top.py
@ -39,7 +39,11 @@ def get():
 	uart0 = uart.UART(0, clk_freq, baud=115200)
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
 	
-	frag = autofragment.from_local()
+	interrupts = Fragment([
+		cpu0.interrupt[0].eq(uart0.events.irq)
+	])
+	
+	frag = autofragment.from_local() + interrupts
 	src_verilog, vns = verilog.convert(frag,
 		{clkfx_sys.clkin, reset0.trigger_reset},
 		name="soc",