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soc/sdram: be more generic in naming

This commit is contained in:
Florent Kermarrec 2015-03-02 11:55:28 +01:00
parent 97331153e0
commit 3465db25a7
2 changed files with 23 additions and 20 deletions
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4
misoclib/mem/sdram/phy/dfii.py
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@ -36,7 +36,9 @@ class PhaseInjector(Module, AutoCSR):
self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata)) self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
class DFIInjector(Module, AutoCSR): class DFIInjector(Module, AutoCSR):
def __init__(self, a, ba, d, nphases=1): def __init__(self, phy, a, ba):
d = phy.settings.dfi_d
nphases = phy.settings.nphases
inti = dfi.Interface(a, ba, d, nphases) inti = dfi.Interface(a, ba, d, nphases)
self.slave = dfi.Interface(a, ba, d, nphases) self.slave = dfi.Interface(a, ba, d, nphases)
self.master = dfi.Interface(a, ba, d, nphases) self.master = dfi.Interface(a, ba, d, nphases)

39
misoclib/soc/sdram.py
View File

@ -1,17 +1,18 @@
from migen.fhdl.std import * from migen.fhdl.std import *
from migen.bus import wishbone, csr from migen.bus import wishbone, csr
from migen.genlib.record import *
from misoclib.mem.sdram.bus import dfi, lasmibus from misoclib.mem.sdram.bus import dfi, lasmibus
from misoclib.mem.sdram.phy import dfii from misoclib.mem.sdram.phy import dfii
from misoclib.mem.sdram.core import minicon, lasmicon from misoclib.mem.sdram.core import minicon, lasmicon
from misoclib.mem.sdram.core.lasmicon import crossbar from misoclib.mem.sdram.core.lasmicon.crossbar import Crossbar
from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
from misoclib.soc import SoC, mem_decoder from misoclib.soc import SoC, mem_decoder
class SDRAMSoC(SoC): class SDRAMSoC(SoC):
csr_map = { csr_map = {
"dfii": 7, "dfii": 7,
"lasmicon": 8, "controller": 8,
"wishbone2lasmi": 9, "wishbone2lasmi": 9,
"memtest_w": 10, "memtest_w": 10,
"memtest_r": 11 "memtest_r": 11
@ -39,24 +40,24 @@ class SDRAMSoC(SoC):
self._sdram_phy_registered = True self._sdram_phy_registered = True
# DFI # DFI
self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a, self.submodules.dfii = dfii.DFIInjector(phy, sdram_geom.mux_a, sdram_geom.bank_a)
phy.settings.dfi_d, phy.settings.nphases) self.comb += Record.connect(self.dfii.master, phy.dfi)
self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy.dfi)
# LASMICON # LASMICON
if self.ramcon_type == "lasmicon": if self.ramcon_type == "lasmicon":
self.submodules.lasmicon = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing) self.submodules.controller = controller = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing)
self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave) self.comb += Record.connect(controller.dfi, self.dfii.slave)
self.submodules.lasmixbar = crossbar.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits) self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits)
if self.with_memtest: if self.with_memtest:
self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master()) self.submodules.memtest_w = memtest.MemtestWriter(crossbar.get_master())
self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master()) self.submodules.memtest_r = memtest.MemtestReader(crossbar.get_master())
if self.with_l2: if self.with_l2:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master()) self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, crossbar.get_master())
sdram_size = 2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8 lasmic = self.controller.lasmic
sdram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size) self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)
# MINICON # MINICON
@ -64,18 +65,18 @@ class SDRAMSoC(SoC):
if self.with_l2: if self.with_l2:
raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))") raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))")
self.submodules.minicon = sdramcon = minicon.Minicon(phy, sdram_geom, sdram_timing) self.submodules.controller = controller = minicon.Minicon(phy, sdram_geom, sdram_timing)
self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave) self.comb += Record.connect(controller.dfi, self.dfii.slave)
sdram_width = flen(sdramcon.bus.dat_r)
sdram_width = flen(controller.bus.dat_r)
sdram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8 sdram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
if sdram_width == 32: if sdram_width == 32:
self.register_mem("sdram", self.mem_map["sdram"], sdramcon.bus, sdram_size) self.register_mem("sdram", self.mem_map["sdram"], controller.bus, sdram_size)
elif sdram_width < 32: elif sdram_width < 32:
self.submodules.dc = wishbone.DownConverter(32, sdram_width) self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width)
self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus) self.comb += Record.connect(downconverter.wishbone_o, controller.bus)
self.register_mem("sdram", self.mem_map["sdram"], self.dc.wishbone_i, sdram_size) self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, sdram_size)
else: else:
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width)) raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
else: else: