soc/cores/spi_mmap: add read only version register

2023-10-19 12:20:22 +11:00 · 2023-10-19 12:20:22 +11:00 · 3477aeaca1
parent 6170c90459
commit 3477aeaca1
1 changed files with 4 additions and 0 deletions
--- a/litex/soc/cores/spi/spi_mmap.py
+++ b/litex/soc/cores/spi/spi_mmap.py
@ -245,6 +245,10 @@ class SPICtrl(LiteXModule):
        self.slot_controls = []
        self.slot_status   = []

+        version = "SPI0"
+        self._version = CSRStatus(size=32, description="""SPI Module Version.""",
+            reset=int.from_bytes(str.encode(version), 'little'))
+
        # Create TX/RX Control/Status registers.
        self.tx_control  = CSRStorage(fields=[
            CSRField("enable", size=1, offset=0, values=[