soc/cores/spi_mmap: add read only version register
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@ -245,6 +245,10 @@ class SPICtrl(LiteXModule):
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self.slot_controls = []
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self.slot_status = []
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version = "SPI0"
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self._version = CSRStatus(size=32, description="""SPI Module Version.""",
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reset=int.from_bytes(str.encode(version), 'little'))
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# Create TX/RX Control/Status registers.
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self.tx_control = CSRStorage(fields=[
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CSRField("enable", size=1, offset=0, values=[
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