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verilog: remove unneeded import

This commit is contained in:
Sebastien Bourdeauducq 2015-09-21 21:19:58 +08:00
parent b8647a161d
commit 34ce6b077f
1 changed files with 1 additions and 1 deletions
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2
migen/fhdl/verilog.py
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@ -5,7 +5,7 @@ from migen.fhdl.structure import *
from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
from migen.fhdl.tools import *
from migen.fhdl.bitcontainer import bits_for, flen
from migen.fhdl.namer import Namespace, build_namespace
from migen.fhdl.namer import build_namespace
from migen.fhdl.conv_output import ConvOutput