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soc/integration/csr_bridge: use registered version only when SDRAM is present.

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Seems to be a good compromise for now.
This commit is contained in:
Florent Kermarrec 2020-08-14 15:29:49 +02:00
parent e4f5dd987e
commit 35929c0f8a
2 changed files with 7 additions and 5 deletions
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9
litex/soc/integration/soc.py
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@ -803,7 +803,7 @@ class SoC(Module):
def add_rom(self, name, origin, size, contents=[]): def add_rom(self, name, origin, size, contents=[]):
self.add_ram(name, origin, size, contents, mode="r") self.add_ram(name, origin, size, contents, mode="r")
def add_csr_bridge(self, origin): def add_csr_bridge(self, origin, register=False):
csr_bridge_cls = { csr_bridge_cls = {
"wishbone": wishbone.Wishbone2CSR, "wishbone": wishbone.Wishbone2CSR,
"axi-lite": axi.AXILite2CSR, "axi-lite": axi.AXILite2CSR,
@ -811,7 +811,8 @@ class SoC(Module):
self.submodules.csr_bridge = csr_bridge_cls( self.submodules.csr_bridge = csr_bridge_cls(
bus_csr = csr_bus.Interface( bus_csr = csr_bus.Interface(
address_width = self.csr.address_width, address_width = self.csr.address_width,
data_width = self.csr.data_width)) data_width = self.csr.data_width),
register = register)
csr_size = 2**(self.csr.address_width + 2) csr_size = 2**(self.csr.address_width + 2)
csr_region = SoCRegion(origin=origin, size=csr_size, cached=False) csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
bus = getattr(self.csr_bridge, self.bus.standard.replace('-', '_')) bus = getattr(self.csr_bridge, self.bus.standard.replace('-', '_'))
@ -910,6 +911,10 @@ class SoC(Module):
"axi-lite": axi.AXILiteInterconnectShared, "axi-lite": axi.AXILiteInterconnectShared,
}[self.bus.standard] }[self.bus.standard]
# SoC CSR bridge ---------------------------------------------------------------------------
# FIXME: for now, use registered CSR bridge when SDRAM is present; find the best compromise.
self.add_csr_bridge(self.mem_map["csr"], register=hasattr(self, "sdram"))
# SoC Bus Interconnect --------------------------------------------------------------------- # SoC Bus Interconnect ---------------------------------------------------------------------
if len(self.bus.masters) and len(self.bus.slaves): if len(self.bus.masters) and len(self.bus.slaves):
# If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint. # If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.

3
litex/soc/integration/soc_core.py
View file

@ -187,9 +187,6 @@ class SoCCore(LiteXSoC):
if timer_uptime: if timer_uptime:
self.timer0.add_uptime() self.timer0.add_uptime()
# Add CSR bridge
self.add_csr_bridge(self.mem_map["csr"])
# Methods -------------------------------------------------------------------------------------- # Methods --------------------------------------------------------------------------------------
def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False): def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):