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Merge pull request #210 from DurandA/master 

Add verilog submodule from CPU cores to manifest
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Tim Ansell 2019-07-03 17:23:36 -07:00 committed by GitHub
parent 4ee9c53f18 68eeba9181
commit 359b8fe4bb
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1 changed files with 4 additions and 1 deletions
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@ -1,5 +1,8 @@
graft litex/build/sim
graft litex/soc/software
graft litex/soc/cores/cpu/lm32/verilog
graft litex/soc/cores/cpu/minerva/verilog
graft litex/soc/cores/cpu/mor1kx/verilog
graft litex/soc/cores/cpu/picorv32/verilog
graft litex/soc/cores/cpu/picorv32/verilog
graft litex/soc/cores/cpu/rocket/verilog
graft litex/soc/cores/cpu/vexriscv/verilog