SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map)
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@ -4,6 +4,7 @@
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# License: BSD
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from math import log2
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import inspect
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from migen import *
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from migen.genlib.record import *
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@ -138,8 +139,8 @@ def soc_sdram_args(parser):
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help="Minimum L2 cache datawidth (default=128)")
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# SDRAM
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parser.add_argument("--max-sdram-size", default=None,
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help="Maximum SDRAM size mapped to the SoC (default=None))")
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parser.add_argument("--max-sdram-size", default=0x40000000,
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help="Maximum SDRAM size mapped to the SoC (default=1GB))")
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def soc_sdram_argdict(args):
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r = soc_core_argdict(args)
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