Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1476 from shenki/riscv-toolchain 

riscv: Fix compilation with new binutils
This commit is contained in:
enjoy-digital 2022-10-30 21:25:18 +01:00 committed by GitHub
parent 7142d25e98 0e2a1b54a4
commit 3704e36c7e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 85 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
litex/soc/cores/cpu/cv32e40p/core.py
View File

@ -22,15 +22,15 @@ CPU_VARIANTS = ["standard", "full"]
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32imc -mabi=ilp32 ",
"full": "-march=rv32imfc -mabi=ilp32 ",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"standard": "-march=rv32i2p0_mc -mabi=ilp32 ",
"full": "-march=rv32i2p0_mfc -mabi=ilp32 ",
}
# OBI / APB / Trace Layouts ------------------------------------------------------------------------

16
litex/soc/cores/cpu/cv32e41p/core.py
View File

@ -22,14 +22,14 @@ CPU_VARIANTS = ["standard"]
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32imc -mabi=ilp32 ",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"standard": "-march=rv32i2p0_mc -mabi=ilp32 ",
}
# OBI / APB / Trace Layouts ------------------------------------------------------------------------

18
litex/soc/cores/cpu/cva5/core.py
View File

@ -20,15 +20,15 @@ CPU_VARIANTS = ["minimal", "standard"]
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"minimal" : "-march=rv32i -mabi=ilp32 ",
"standard" : "-march=rv32im -mabi=ilp32 ",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"minimal" : "-march=rv32i2p0 -mabi=ilp32 ",
"standard" : "-march=rv32i2p0_m -mabi=ilp32 ",
}
# CVA5 ----------------------------------------------------------------------------------------------

28
litex/soc/cores/cpu/femtorv/core.py
View File

@ -26,20 +26,20 @@ CPU_VARIANTS = {
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32i -mabi=ilp32",
"quark": "-march=rv32i -mabi=ilp32",
"tachyon": "-march=rv32i -mabi=ilp32",
"electron": "-march=rv32im -mabi=ilp32",
"intermissum": "-march=rv32im -mabi=ilp32",
"gracilis": "-march=rv32imc -mabi=ilp32",
"petitbateau": "-march=rv32imfc -mabi=ilp32f",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"standard": "-march=rv32i2p0 -mabi=ilp32",
"quark": "-march=rv32i2p0 -mabi=ilp32",
"tachyon": "-march=rv32i2p0 -mabi=ilp32",
"electron": "-march=rv32i2p0_m -mabi=ilp32",
"intermissum": "-march=rv32i2p0_m -mabi=ilp32",
"gracilis": "-march=rv32i2p0_mc -mabi=ilp32",
"petitbateau": "-march=rv32i2p0_mfc -mabi=ilp32f",
}
# FemtoRV ------------------------------------------------------------------------------------------

16
litex/soc/cores/cpu/firev/core.py
View File

@ -20,14 +20,14 @@ CPU_VARIANTS = {
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32i -mabi=ilp32",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"standard": "-march=rv32i2p0 -mabi=ilp32",
}
# FireV ------------------------------------------------------------------------------------------

16
litex/soc/cores/cpu/ibex/core.py
View File

@ -22,14 +22,14 @@ CPU_VARIANTS = ["standard"]
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32imc -mabi=ilp32 ",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"standard": "-march=rv32i2p0_mc -mabi=ilp32 ",
}
# OBI <> Wishbone ----------------------------------------------------------------------------------

22
litex/soc/cores/cpu/neorv32/core.py
View File

@ -20,17 +20,17 @@ CPU_VARIANTS = ["minimal", "lite", "standard", "full"]
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"minimal": "-march=rv32i -mabi=ilp32",
"lite": "-march=rv32imc -mabi=ilp32",
"standard": "-march=rv32imc -mabi=ilp32",
"full": "-march=rv32imc -mabi=ilp32",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"minimal": "-march=rv32i2p0 -mabi=ilp32",
"lite": "-march=rv32i2p0_mc -mabi=ilp32",
"standard": "-march=rv32i2p0_mc -mabi=ilp32",
"full": "-march=rv32i2p0_mc -mabi=ilp32",
}
# NEORV32 ------------------------------------------------------------------------------------------

18
litex/soc/cores/cpu/picorv32/core.py
View File

@ -23,15 +23,15 @@ CPU_VARIANTS = ["minimal", "standard"]
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"minimal": "-march=rv32i -mabi=ilp32 ",
"standard": "-march=rv32im -mabi=ilp32 ",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"minimal": "-march=rv32i2p0 -mabi=ilp32 ",
"standard": "-march=rv32i2p0_m -mabi=ilp32 ",
}
# PicoRV32 -----------------------------------------------------------------------------------------

18
litex/soc/cores/cpu/serv/core.py
View File

@ -20,15 +20,15 @@ CPU_VARIANTS = ["standard", "mdu"]
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32i -mabi=ilp32",
"mdu": "-march=rv32im -mabi=ilp32",
# /------------ Base ISA
# | /------- Hardware Multiply + Divide
# | |/----- Atomics
# | ||/---- Compressed ISA
# | |||/--- Single-Precision Floating-Point
# | ||||/-- Double-Precision Floating-Point
# i macfd
"standard": "-march=rv32i2p0 -mabi=ilp32",
"mdu": "-march=rv32i2p0_m -mabi=ilp32",
}
# SERV ---------------------------------------------------------------------------------------------