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soc/cores/hyperbus: Simplify Clk Generation.

This commit is contained in:
Florent Kermarrec 2024-08-21 17:10:36 +02:00
parent ecd9eee5a4
commit 37823e34b6
1 changed files with 2 additions and 5 deletions
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7
litex/soc/cores/hyperbus.py
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@ -142,14 +142,11 @@ class HyperRAM(LiteXModule):
# Burst Timer ------------------------------------------------------------------------------ # Burst Timer ------------------------------------------------------------------------------
self.burst_timer = burst_timer = WaitTimer(sys_clk_freq * self.tCSM) self.burst_timer = burst_timer = WaitTimer(sys_clk_freq * self.tCSM)
# Clock Generation (sys_clk/4) ------------------------------------------------------------- # Clk Generation ---------------------------------------------------------------------------
self.sync_io += [ self.sync_io += [
clk_phase.eq(0b00),
If(cs, If(cs,
# Increment Clk Phase on CS.
clk_phase.eq(clk_phase + 1) clk_phase.eq(clk_phase + 1)
).Else(
# Else set Clk Phase to default value.
clk_phase.eq(0b00)
) )
] ]
cases = { cases = {