soc/add_sdram: add sdram csr
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@ -905,6 +905,7 @@ class LiteXSoC(SoC):
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timing_settings = module.timing_settings,
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timing_settings = module.timing_settings,
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clk_freq = self.sys_clk_freq,
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clk_freq = self.sys_clk_freq,
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**kwargs)
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**kwargs)
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self.csr.add("sdram")
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# LiteDRAM port ----------------------------------------------------------------------------
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# LiteDRAM port ----------------------------------------------------------------------------
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port = self.sdram.crossbar.get_port()
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port = self.sdram.crossbar.get_port()
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@ -18,12 +18,6 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
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# SoCSDRAM -----------------------------------------------------------------------------------------
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# SoCSDRAM -----------------------------------------------------------------------------------------
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class SoCSDRAM(SoCCore):
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class SoCSDRAM(SoCCore):
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csr_map = {
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"sdram": 8,
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"l2_cache": 9,
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}
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csr_map.update(SoCCore.csr_map)
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def __init__(self, platform, clk_freq,
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def __init__(self, platform, clk_freq,
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l2_size = 8192,
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l2_size = 8192,
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l2_reverse = True,
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l2_reverse = True,
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