test bist at high speed(working)
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@ -27,9 +27,9 @@ class SATABIST(Module):
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fsm.act("IDLE",
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self.done.eq(1),
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counter.reset.eq(1),
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If(self.start,
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self.ctrl_error_counter.reset.eq(1),
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self.data_error_counter.reset.eq(1),
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If(self.start,
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NextState("SEND_WRITE_CMD_AND_DATA")
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)
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)
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@ -268,29 +268,63 @@ class CommandGenerator(Module, AutoCSR):
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class BIST(Module, AutoCSR):
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def __init__(self, sata_con, sector_size):
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self._start = CSR()
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self._sector = CSRStorage(48)
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self._count = CSRStorage(4)
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self._done = CSRStatus()
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self._stop = CSR()
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self._sector = CSRStatus(48)
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self._ctrl_errors = CSRStatus(32)
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self._data_errors = CSRStatus(32)
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check_prepare = Signal()
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sector = self._sector.status
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ctrl_errors = self._ctrl_errors.status
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data_errors = self._data_errors.status
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###
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self.sata_bist = SATABIST(sector_size)
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self.comb += [
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Record.connect(self.sata_bist.source, sata_con.sink),
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Record.connect(sata_con.source, self.sata_bist.sink),
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self.sata_bist.start.eq(self._start.r & self._start.re),
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self.sata_bist.sector.eq(self._sector.storage),
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self.sata_bist.count.eq(self._count.storage),
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self._done.status.eq(self.sata_bist.done),
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self._ctrl_errors.status.eq(self.sata_bist.ctrl_errors),
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self._data_errors.status.eq(self.sata_bist.data_errors),
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Record.connect(self.sata_bist.source, sata_con.sink)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.comb += [
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self.sata_bist.sector.eq(sector),
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self.sata_bist.count.eq(4)
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]
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# FSM
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fsm.act("IDLE",
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If(self._start.r & self._start.re,
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NextState("START")
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)
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)
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fsm.act("START",
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self.sata_bist.start.eq(1),
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NextState("WAIT_DONE")
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)
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fsm.act("WAIT_DONE",
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If(self.sata_bist.done,
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NextState("CHECK_PREPARE")
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).Elif(self._stop.r & self._stop.re,
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NextState("IDLE")
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)
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)
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fsm.act("CHECK_PREPARE",
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check_prepare.eq(1),
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NextState("START")
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)
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self.sync += [
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If(check_prepare,
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ctrl_errors.eq(ctrl_errors + self.sata_bist.ctrl_errors),
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data_errors.eq(data_errors + self.sata_bist.data_errors),
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sector.eq(sector+4)
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)
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]
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class TestDesign(UART2WB, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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@ -2,24 +2,21 @@ import time
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from config import *
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from tools import *
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sector_size = 512
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wb.open()
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regs = wb.regs
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###
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i = 0
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data_errors = 0
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ctrl_errors = 0
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regs.bist_start.write(1)
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last_sector = 0
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while True:
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regs.bist_sector.write(i)
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regs.bist_count.write(4)
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regs.bist_start.write(1)
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while (regs.bist_done.read() != 1):
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time.sleep(0.01)
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data_errors += regs.bist_data_errors.read()
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ctrl_errors += regs.bist_ctrl_errors.read()
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if i%10 == 0:
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print("sector %08d / data_errors %0d / ctrl_errors %d " %(i, data_errors, ctrl_errors))
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data_errors = 0
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ctrl_errors = 0
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i += 1
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time.sleep(1)
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sector = regs.bist_sector.read()
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n_sectors = sector - last_sector
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last_sector = sector
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n_bytes = n_sectors*sector_size*4*2
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ctrl_errors = regs.bist_ctrl_errors.read()
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data_errors = regs.bist_data_errors.read()
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print("%04d MB/s / data_errors %08d / ctrl_errors %08d " %(n_bytes/(1024*1024), data_errors, ctrl_errors))
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###
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wb.close()
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