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test/test_hyperbus: Update.

This commit is contained in:
Florent Kermarrec 2024-04-16 11:12:30 +02:00
parent a44b7944ca
commit 3978af9c39
1 changed files with 6 additions and 6 deletions
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12
test/test_hyperbus.py
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@ -56,7 +56,7 @@ class TestHyperBus(unittest.TestCase):
self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o)) self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
yield yield
dut = HyperRAM(HyperRamPads(), latency=5) dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed")
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def test_hyperram_write_latency_6_2x(self): def test_hyperram_write_latency_6_2x(self):
@ -82,7 +82,7 @@ class TestHyperBus(unittest.TestCase):
self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o)) self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
yield yield
dut = HyperRAM(HyperRamPads(), latency=6) dut = HyperRAM(HyperRamPads(), latency=6, latency_mode="fixed")
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def test_hyperram_write_latency_7_2x(self): def test_hyperram_write_latency_7_2x(self):
@ -108,7 +108,7 @@ class TestHyperBus(unittest.TestCase):
self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o)) self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
yield yield
dut = HyperRAM(HyperRamPads(), latency=7) dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="fixed")
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def test_hyperram_write_latency_7_1x(self): def test_hyperram_write_latency_7_1x(self):
@ -162,7 +162,7 @@ class TestHyperBus(unittest.TestCase):
self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe)) self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
yield yield
dut = HyperRAM(HyperRamPads(), latency=5) dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed")
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def test_hyperram_read_latency_6_2x(self): def test_hyperram_read_latency_6_2x(self):
@ -190,7 +190,7 @@ class TestHyperBus(unittest.TestCase):
self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe)) self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
yield yield
dut = HyperRAM(HyperRamPads(), latency=6) dut = HyperRAM(HyperRamPads(), latency=6, latency_mode="fixed")
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def test_hyperram_read_latency_7_2x(self): def test_hyperram_read_latency_7_2x(self):
@ -218,7 +218,7 @@ class TestHyperBus(unittest.TestCase):
self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe)) self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
yield yield
dut = HyperRAM(HyperRamPads(), latency=7) dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="fixed")
run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd") run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
def test_hyperram_read_latency_7_1x(self): def test_hyperram_read_latency_7_1x(self):