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soc/add_uart: fix bridge

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This commit is contained in:
Florent Kermarrec 2020-02-11 16:55:37 +01:00
parent 160c55d1d4
commit 399b65fa17
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc.py
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@ -876,7 +876,7 @@ class LiteXSoC(SoC):
pads = self.platform.request("serial"),
clk_freq = self.sys_clk_freq,
baudrate = baudrate)
self.bus.master(name="uart_bridge", master=self.uart.wishbone)
self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
elif name == "crossover":
self.submodules.uart = uart.UARTCrossover()
else: