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dvisampler: fixes

This commit is contained in:
Sebastien Bourdeauducq 2013-03-17 15:41:50 +01:00
parent 9f02ced39e
commit 3a0cf278fd
2 changed files with 12 additions and 12 deletions
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20
milkymist/dvisampler/clocking.py
View File

@ -13,9 +13,9 @@ class Clocking(Module, AutoReg):
self.locked = Signal()
self.serdesstrobe = Signal()
self._cd_pix = ClockDomain()
self._cd_pix5x = ClockDomain()
self._cd_pix20x = ClockDomain()
self.clock_domains._cd_pix = ClockDomain()
self.clock_domains._cd_pix5x = ClockDomain()
self.clock_domains._cd_pix20x = ClockDomain()
###
@ -27,9 +27,9 @@ class Clocking(Module, AutoReg):
self.specials += Instance("PLL_BASE",
Instance.Parameter("CLKIN_PERIOD", 22.0),
Instance.Parameter("CLKFBOUT_MULT", 20),
Instance.Parameter("CLKOUT0_DIVIDE", 20), # pix
Instance.Parameter("CLKOUT0_DIVIDE", 1), # pix20x
Instance.Parameter("CLKOUT1_DIVIDE", 4), # pix5x
Instance.Parameter("CLKOUT2_DIVIDE", 1), # pix20x
Instance.Parameter("CLKOUT2_DIVIDE", 20), # pix
Instance.Parameter("COMPENSATION", "INTERNAL"),
Instance.Output("CLKFBOUT", clkfbout),
@ -42,14 +42,10 @@ class Clocking(Module, AutoReg):
Instance.Input("RST", self._r_pll_reset.field.r)
)
self.specials += Instance("BUFG",
Instance.Input("I", pll_clk0), Instance.Output("O", self._cd_pix.clk))
self.specials += Instance("BUFG",
Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
locked_async = Signal()
self.specials += Instance("BUFPLL",
Instance.Parameter("DIVIDE", 4),
Instance.Input("PLLIN", pll_clk2),
Instance.Input("PLLIN", pll_clk0),
Instance.ClockPort("GCLK", "pix5x"),
Instance.Input("LOCKED", pll_locked),
Instance.Output("IOCLK", self._cd_pix20x.clk),
@ -58,3 +54,7 @@ class Clocking(Module, AutoReg):
)
self.specials += MultiReg(locked_async, self.locked, "sys")
self.comb += self._r_locked.field.w.eq(self.locked)
self.specials += Instance("BUFG",
Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
self.specials += Instance("BUFG",
Instance.Input("I", pll_clk2), Instance.Output("O", self._cd_pix.clk))

4
milkymist/dvisampler/datacapture.py
View File

@ -24,10 +24,10 @@ class DataCapture(Module, AutoReg):
delay_ce = Signal()
delay_rst = Signal()
delay_init = Signal()
self.specials += Instance("IDELAY2",
self.specials += Instance("IODELAY2",
Instance.Parameter("DELAY_SRC", "IDATAIN"),
Instance.Parameter("IDELAY_TYPE", "VARIABLE_FROM_ZERO"),
Instance.Parameter("COUNTER_WRAP_AROUND", "STAY_AT_LIMIT"),
Instance.Parameter("COUNTER_WRAPAROUND", "STAY_AT_LIMIT"),
Instance.Input("IDATAIN", self.pad),
Instance.Output("DATAOUT", pad_delayed),
Instance.Input("INC", delay_inc | delay_init),