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soc/add_pcie: Remove csr_ordering parameter (not useful and remove on litepcie).

This commit is contained in:
Florent Kermarrec 2023-07-12 19:42:54 +02:00
parent f9e32eb3eb
commit 3a2586c48b
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc.py
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@ -2012,7 +2012,7 @@ class LiteXSoC(SoC):
if msi_type == "msi-multi-vector":
msi = LitePCIeMSIMultiVector(width=msi_width)
if msi_type == "msi-x":
msi = LitePCIeMSIX(endpoint=self.pcie_endpoint, width=msi_width, csr_ordering=self.csr.ordering)
msi = LitePCIeMSIX(endpoint=self.pcie_endpoint, width=msi_width)
self.add_module(name=f"{name}_msi", module=msi)
# FIXME: On Ultrascale/Ultrascale+ limit rate of IRQs to 1MHz (to prevent issue with
# IRQs stalled).