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software/liblitespi/spiflash: fix clk_freq tuning with L2 cache

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Correct CRC was always calculated, regardless of divisor, as the
test flash block was in the L2 cache. This resulted in the minimum
divisor being used and incorrect flash reads with 200MHz sys_clock.
This commit is contained in:
Andrew Dennison 2024-02-01 10:14:20 +11:00
parent e0416639f7
commit 3a890a077b
1 changed files with 4 additions and 0 deletions
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4
litex/soc/software/liblitespi/spiflash.c
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@ -25,6 +25,8 @@ int spiflash_freq_init(void)
unsigned int lowest_div, crc, crc_test;
lowest_div = spiflash_phy_clk_divisor_read();
flush_cpu_dcache();
flush_l2_cache();
crc = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE);
crc_test = crc;
@ -40,6 +42,8 @@ int spiflash_freq_init(void)
while((crc == crc_test) && (lowest_div-- > 0)) {
spiflash_phy_clk_divisor_write((uint32_t)lowest_div);
flush_cpu_dcache();
flush_l2_cache();
crc_test = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE);
#ifdef SPIFLASH_DEBUG
printf("[DIV: %d] %08x\n\r", lowest_div, crc_test);