cva6_wrapper: Fix reset logic

Without this, reset was never being asserted which caused problems on
hardware (probably because the CPU started running while the rest of the
SoC had reset asserted...)

Signed-off-by: gatecat <gatecat@ds0.me>

litex/soc/cores/cpu/cva6/cva6_wrapper/cva6_wrapper.sv

@@ -140,7 +140,7 @@ logic [1:0] irq;
 assign test_en    = 1'b0;
 
 always @(posedge clk_i)
-    ndmreset_n <= ~ndmreset || rst_n;
+    ndmreset_n <= ~ndmreset && rst_n;
 
 // ---------------
 // AXI Xbar