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README: Add link to the Wiki in the Welcome section.

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Florent Kermarrec 2021-02-12 13:40:11 +01:00
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@ -14,6 +14,8 @@ The common components of a SoC are provided directly: Buses and Streams (Wishbon
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
SoC builder to create/develop/debug FPGA SoCs in Python. SoC builder to create/develop/debug FPGA SoCs in Python.
**Want to get started and/or looking for documentation? Make sure to visit the [Wiki](https://github.com/enjoy-digital/litex/wiki)!**
**A question or want to get in touch? Our IRC channel is [#litex at freenode.net](https://webchat.freenode.net/?channels=litex)** **A question or want to get in touch? Our IRC channel is [#litex at freenode.net](https://webchat.freenode.net/?channels=litex)**
# Typical LiteX design flow: # Typical LiteX design flow: