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build/xilinx/vivado: ensure Vivado process our .xdc early. 

When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.

Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
This commit is contained in:
Florent Kermarrec 2020-05-06 13:13:01 +02:00
parent b057858071
commit 3c34039b73
1 changed files with 2 additions and 1 deletions
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3
litex/build/xilinx/vivado.py
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@ -167,6 +167,7 @@ class XilinxVivadoToolchain:
# Add constraints # Add constraints
tcl.append("\n# Add constraints\n") tcl.append("\n# Add constraints\n")
tcl.append("read_xdc {}.xdc".format(build_name)) tcl.append("read_xdc {}.xdc".format(build_name))
tcl.append("set_property PROCESSING_ORDER EARLY [get_files {}.xdc]".format(build_name))
# Add pre-synthesis commands # Add pre-synthesis commands
tcl.append("\n# Add pre-synthesis commands\n") tcl.append("\n# Add pre-synthesis commands\n")
@ -276,7 +277,7 @@ class XilinxVivadoToolchain:
"-to [get_pins -filter {{REF_PIN_NAME == PRE}} " "-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]" "-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
) )
# clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs # clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs
platform.add_platform_command( platform.add_platform_command(
"set_max_delay 2 -quiet " "set_max_delay 2 -quiet "
"-from [get_pins -filter {{REF_PIN_NAME == C}} " "-from [get_pins -filter {{REF_PIN_NAME == C}} "