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gen/fhdl/verilog: explicitly define input/output/inout wires. 

When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
This commit is contained in:
Florent Kermarrec 2020-05-05 16:58:33 +02:00
parent 0aa3c339cc
commit b057858071
1 changed files with 3 additions and 3 deletions
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6
litex/gen/fhdl/verilog.py
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@ -236,17 +236,17 @@ def _printheader(f, ios, name, ns, attr_translate,
sig.type = "wire"
if sig in inouts:
sig.direction = "inout"
r += "\tinout " + _printsig(ns, sig)
r += "\tinout wire " + _printsig(ns, sig)
elif sig in targets:
sig.direction = "output"
if sig in wires:
r += "\toutput " + _printsig(ns, sig)
r += "\toutput wire " + _printsig(ns, sig)
else:
sig.type = "reg"
r += "\toutput reg " + _printsig(ns, sig)
else:
sig.direction = "input"
r += "\tinput " + _printsig(ns, sig)
r += "\tinput wire " + _printsig(ns, sig)
r += "\n);\n\n"
for sig in sorted(sigs - ios, key=lambda x: x.duid):
attr = _printattr(sig.attr, attr_translate)