build/xilinx/vivado: ensure Vivado process our .xdc early.

When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.

Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.

litex/build/xilinx/vivado.py

@@ -167,6 +167,7 @@ class XilinxVivadoToolchain:
         # Add constraints
         tcl.append("\n# Add constraints\n")
         tcl.append("read_xdc {}.xdc".format(build_name))
+        tcl.append("set_property PROCESSING_ORDER EARLY [get_files {}.xdc]".format(build_name))
 
         # Add pre-synthesis commands
         tcl.append("\n# Add pre-synthesis commands\n")