cores/dma: End transfer when the last flag is set.

2022-09-10 10:15:23 +02:00 · 2022-09-10 10:15:23 +02:00 · 3c4c12a72f
parent 6ad6d1e414
commit 3c4c12a72f
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@ -187,7 +187,7 @@ class WishboneDMAWriter(Module, AutoCSR):
        )
        fsm.act("RUN",
            self._sink.valid.eq(self.sink.valid),
-            self._sink.last.eq(offset == (length - 1)),
+            self._sink.last.eq(self.sink.last | (offset + 1 == length)),
            self._sink.address.eq(base + offset),
            self._sink.data.eq(self.sink.data),
            self.sink.ready.eq(self._sink.ready),