cores/dma: Don’t drop data while idle.

2022-09-10 10:13:18 +02:00 · 2022-09-10 10:13:18 +02:00 · 6ad6d1e414
parent 15f72174ce
commit 6ad6d1e414
1 changed files with 0 additions and 1 deletions
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@ -182,7 +182,6 @@ class WishboneDMAWriter(Module, AutoCSR):
        self.submodules += fsm
        self.comb += fsm.reset.eq(~self._enable.storage)
        fsm.act("IDLE",
-            self.sink.ready.eq(1),
            NextValue(offset, 0),
            NextState("RUN"),
        )