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litex: adding explicit clk signal to ODDR/IDDR models in DDRTristate

This commit is contained in:
Pawel Sagan 2021-09-01 16:54:53 +02:00
parent 25e0153dd5
commit 3cf6126663
1 changed files with 3 additions and 3 deletions
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6
litex/build/xilinx/common.py
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@ -159,9 +159,9 @@ class XilinxDDRTristateImpl(Module):
_o = Signal() _o = Signal()
_oe_n = Signal() _oe_n = Signal()
_i = Signal() _i = Signal()
self.specials += DDROutput(i1, i2, _o) self.specials += DDROutput(i1, i2, _o, clk)
self.specials += DDROutput(~oe1, ~oe2, _oe_n) self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk)
self.specials += DDRInput(_i, o1, o2) self.specials += DDRInput(_i, o1, o2, clk)
self.specials += Instance("IOBUF", self.specials += Instance("IOBUF",
io_IO = io, io_IO = io,
o_O = _i, o_O = _i,